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/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
/gem5/ext/dnet/
H A Dip.h12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
/gem5/src/sim/
H A Demul_driver.hh13995:5d459168a680 Tue Aug 28 10:13:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
11624:9796e43e751d Tue Sep 13 23:12:00 EDT 2016 Michael LeBeane <michael.lebeane@amd.com> sim, syscall_emul: Add mmap to EmulatedDriver
Add support for calling mmap on an EmulatedDriver file descriptor.
H A DDVFSHandler.py10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
/gem5/src/arch/mips/linux/
H A Dlinux.cc11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/
H A Dsimout11959:c000bfbbdadd Thu Mar 30 20:59:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the stats for 70.twolf for x86 o3-timing mode.

The following CL changed the stats:

commit 43418e7f81099072fb7d56dae11110ae1d858162
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 13:07:43 2017 -0600

syscall-emul: Move memState into its own file

It would be a good idea to try to figure out why, since it doesn't *look* like
this change was intended to move things around in memory or otherwise change
simulated behavior.

Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63
Reviewed-on: https://gem5-review.googlesource.com/2655
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9901:13c5fea24be1 Wed Oct 02 05:03:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> stats: Update x86 stats after x87 fixes

The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
9039:9a22621c741c Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Update stats for the CPUID change.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/src/mem/ruby/common/
H A DSubBlock.hh6204:b247610d8882 Wed May 13 01:33:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: remove random uint typedef and use unsigned
6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/power/linux/
H A Dlinux.hh11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
/gem5/src/arch/alpha/linux/
H A Dlinux.cc11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
/gem5/src/mem/ruby/profiler/
H A DStoreTrace.cc6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6149:ff34514cbf37 Mon May 11 13:38:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: Renamed Ruby's EventQueue to RubyEventQueue
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
11156:a37dda0f0202 Mon Oct 05 14:13:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update SMT tests to correctly configure CPUs

The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
/gem5/src/base/
H A Ddebug.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8231:51cf7f3cf9ac Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> debug: create a Debug namespace
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/dev/storage/
H A Dide_disk.cc12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
11980:56d16946ed95 Mon Apr 24 09:55:00 EDT 2017 Jason Lowe-Power <jason@lowepower.com> dev: Add ATA command used in recent Linux kernels

Add a case for the ATA command ATAPI_IDENTIFY_DEVICE.
This avoids the panic: Unsupported ATA command when booting a recent Linux
kernel. This was tested on 4.8.13.

Change-Id: Ib297a2c02da0730d8698c59801254dd0f5ee9f7f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/2863
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
/gem5/src/arch/arm/
H A Dsemihosting.hh12533:a5b047f55eb6 Tue Feb 13 13:03:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Add support for secure state in semihosting

The semihosting component currently issues non-secure memory accesses
using the standard port proxy. This doesn't work when the guest is
running in secure state.

Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8365
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
12533:a5b047f55eb6 Tue Feb 13 13:03:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Add support for secure state in semihosting

The semihosting component currently issues non-secure memory accesses
using the standard port proxy. This doesn't work when the guest is
running in secure state.

Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8365
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
12531:3141027bd11a Thu Feb 08 15:13:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Add aarch64 semihosting support

Add basic support for Arm Semihosting 2.0 simulation calls [1]. These
calls let the guest system call a simulator or debugger to request
OS-like support when running bare metal code.

With the exception of SYS_SYSTEM, this implementation supports all of
the Semihosting 2.0 specification in aarch64.

[1] https://developer.arm.com/docs/100863/latest/preface

Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8147
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/tests/configs/
H A Dgpu-ruby.py12581:a8f1d31d3492 Tue Mar 13 12:13:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> tests: Add missing print replacements in tests subdir

Some python files were still using deprecated print statement.

Change-Id: I19b1fe9c28650707f01725d40c87ad0538f9c5e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9141
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
12581:a8f1d31d3492 Tue Mar 13 12:13:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> tests: Add missing print replacements in tests subdir

Some python files were still using deprecated print statement.

Change-Id: I19b1fe9c28650707f01725d40c87ad0538f9c5e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9141
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
11670:6ce719503eae Thu Oct 13 03:17:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> ruby: Fix regressions and make Ruby configs Python packages

This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.

As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.
/gem5/src/cpu/
H A Dstatic_inst_fwd.hh10276:4cbfdcdb2144 Wed Aug 13 06:57:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> cpu: Don't forward declare RefCountingPtr

RefCountingPtr is sometimes forward declared to avoid having to
include refcnt.hh. This does not work since we typically return
instances of RefCountingPtr rather than references to instances. The
only reason this currently works is that we include refcnt.hh in
cprintf.hh, which "leaks" the header to most other source files. This
changeset replaces such forward declarations with an include of
refcnt.hh.
/gem5/src/dev/alpha/
H A Dtsunamireg.h4059:e9cef915589f Tue Feb 13 15:58:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make mulitple consoles work and be distinguishable from each other

src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
/gem5/build_opts/
H A DNULL9850:87d6b41749e9 Wed Sep 04 13:22:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
/gem5/src/arch/alpha/
H A DAlphaISA.py9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
/gem5/src/arch/arm/isa/insts/
H A Dmult.isa8304:16911ff780d3 Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Construct the predicate test register for more instruction programatically.

If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register.

Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd.

This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
/gem5/src/arch/mips/
H A DMipsISA.py9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
H A DSConsopts5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Ddt_constants.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dpra_constants.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/power/
H A Dmiscregs.hh7512:ffac9df60637 Thu Jul 22 13:54:00 EDT 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> Power: The condition register should be set or cleared upon a system call
return to indicate success or failure.

Completed in 75 milliseconds

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