Searched hist:13 (Results 226 - 250 of 1864) sorted by relevance
/gem5/src/arch/power/ | ||
H A D | kernel_stats.hh | 8790:0dc424619109 Sun Nov 13 03:40:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stub kernel_stats.hh. |
/gem5/src/arch/sparc/ | ||
H A D | locked_mem.hh | 12218:8c5db15dc8e7 Tue Jun 13 06:14:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Signal the local monitor when clearing the global monitor ARM systems require the coordination of the global and local monitors. When the system is run without caches the global monitor is implemented in the abstract memory object. This change adds a callback from the abstract memory that notifies the local monitor when the global monitor is cleared. Additionally, for ARM systems the local monitor signals the event register and wakes the thread context up. Subsequent wait-for-event (WFE) instructions will be immediately signaled. Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3760 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> 9383:55fa95053ee8 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> o3: Fix issue with LLSC ordering and speculation This patch unlocks the cpu-local monitor when the CPU sees a snoop to a locked address. Previously we relied on the cache to handle the locking for us, however some users on the gem5 mailing list reported a case where the cpu speculatively executes a ll operation after a pending sc operation in the pipeline and that makes the cache monitor valid. This should handle that case by invaliding the local monitor. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 3170:37fd1e73f836 Sun Oct 08 13:53:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. |
/gem5/src/mem/ruby/common/ | ||
H A D | BoolVec.hh | 11208:fa3e56b6e0b6 Fri Nov 13 17:30:00 EST 2015 Joe Gross <joseph.gross@amd.com> ruby: add BoolVec The BoolVec typedef and insertion operator overload function simplify usage of vectors of type bool |
/gem5/src/mem/cache/prefetch/ | ||
H A D | signature_path_v2.hh | 13624:3d8220c2d41d Thu Dec 13 05:38:00 EST 2018 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Updated version of the Signature Path Prefetcher This implementation is based in the description available in: Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. 2016. Path confidence based lookahead prefetching. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages. Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9 Reviewed-on: https://gem5-review.googlesource.com/c/14819 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/python/ | ||
H A D | marshal.cc | 13730:2c34d4c9089b Wed Feb 13 06:32:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> scons: Marshal Python sources using the same Python as gem5 We currently use the Python version used by scons to marshal Python code. This doesn't work when building gem5 with Python 3 support since scons typically runs in Python 2.7. Add a custom marshal helper that links with the same library as gem5 to generate byte code that is guaranteed to work in gem5's Python interpreter. Change-Id: I665b0f2078726d4c055d74a3e668a580fc613b59 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16422 Reviewed-by: Gabe Black <gabeblack@google.com> |
/gem5/src/cpu/pred/ | ||
H A D | multiperspective_perceptron_64KB.cc | 14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | multiperspective_perceptron_64KB.hh | 14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | multiperspective_perceptron_8KB.cc | 14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | multiperspective_perceptron_8KB.hh | 14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/mem/cache/compressors/ | ||
H A D | bdi.hh | 13944:5000533e6b81 Wed Jun 13 10:39:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create BDI Compressor Implement Base-Delta-Immediate compression, as described in 'Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches' Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/proto/ | ||
H A D | protoio.hh | 9399:f7582cce2459 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> base: Add wrapped protobuf input stream This patch adds support for inputting protobuf messages through a ProtoInputStream which hides the internal streams used by the library. The stream is created based on the name of an input file and optionally includes decompression using gzip. The input stream will start by getting a magic number from the file, and also verify that it matches with the expected value. Once opened, messages can be read incrementally from the stream, returning true/false until an error occurs or the end of the file is reached. 9397:6e6b8d8ab258 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> base: Add wrapped protobuf output streams This patch adds support for outputting protobuf messages through a ProtoOutputStream which hides the internal streams used by the library. The stream is created based on the name of an output file and optionally includes compression using gzip. The output stream will start by putting a magic number in the file, and then for every message that is serialized prepend the size such that the stream can be written and read incrementally. At this point this merely serves as a proof of concept. |
/gem5/src/arch/mips/ | ||
H A D | system.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
H A D | vtophys.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
/gem5/src/arch/x86/isa/insts/ | ||
H A D | __init__.py | 5680:39ae093fb4eb Mon Oct 13 01:42:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement entering an interrupt in microcode. 4529:5f32651bc10e Fri Jun 08 12:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move the microcode assembly to a python package instead of isa_parser files. Also, the code is now a single string which runs through the microcode assembler rather than docstrings associated with classes named after each architectural level instruction. |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/ | ||
H A D | simerr | 9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes. 8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor |
/gem5/tests/long/se/20.parser/ref/arm/linux/minor-timing/ | ||
H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes |
/gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/ | ||
H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/ | ||
H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/ | ||
H A D | config.ini | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/ | ||
H A D | config.ini | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/ | ||
H A D | config.ini | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/ | ||
H A D | config.ini | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
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