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/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/
H A Dsimout9039:9a22621c741c Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Update stats for the CPUID change.
/gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/
H A Dstats.txt11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/
H A Dstats.txt11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/
H A Dstats.txt11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/
H A Dstats.txt11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/
H A Dstats.txt11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
/gem5/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/
H A Dstats.txt11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
/gem5/src/dev/arm/
H A Dflash_device.hh10801:049eb85e8ea2 Thu Apr 23 13:37:00 EDT 2015 Rene de Jong <rene.dejong@arm.com> arm, dev: Add a NAND flash timing model

This adds a NAND flash timing model. This model takes the number of
planes into account and is ultimately intended to be used as a
high-level performance model for any device using flash. To access the
memory, use either readMemory or writeMemory.

To make use of the model you will need an interface model
such as UFSHostDevice, which is part of a separate patch.

At the moment the flash device is part of the ARM device tree since
the only use if the UFSHostDevice, and that in turn relies on the ARM
GIC.
/gem5/src/arch/generic/
H A DSConscript9850:87d6b41749e9 Wed Sep 04 13:22:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
/gem5/src/arch/x86/isa/formats/
H A Dformats.isa4323:13ca4002d2ac Tue Apr 03 11:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
H A Dcpuid.isa9038:d7ddf3266d46 Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Ensure that the CPUID instruction always writes its outputs.

The CPUID instruction was implemented so that it would only write its results
if the instruction was successful. This works fine on the simple CPU where
unwritten registers retain their old values, but on a CPU like O3 with
renaming this is broken. The instruction needs to write the old values back
into the registers explicitly if they aren't being changed.
/gem5/util/tlm/
H A DREADME11832:4d1f9823013a Mon Feb 13 15:25:00 EST 2017 Christian Menard <Christian.Menard@tu-dresden.de> misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Update the README
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/
H A Dstats.txt11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/src/arch/mips/
H A Dpagetable.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/x86/
H A Demulenv.cc5616:05fd71ca96db Fri Oct 10 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> misc: remove #include <cassert> from misc.hh since not everyone needs it.
H A Dvtophys.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
H A Disa_traits.hh10835:d4b162a57400 Fri May 15 13:39:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Appease gcc 5.1

Three minor issues are resolved:

1. Apparently gcc 5.1 does not like negation of booleans followed by
bitwise AND.

2. Somehow the compiler also gets confused and warns about
NoopMachInst being unused (removing it causes compilation errors
though). Most likely a compiler bug.

3. There seems to be a number of instances where loop unrolling causes
false positives for the array-bounds check. For now, switch to
std::array. Potentially we could disable the warning for newer gcc
versions, but switching to std::array is probably a good move in
any case.
9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change.
9040:cdfe09f9bdee Mon Jun 04 13:57:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

This eliminates a use of the ExtMachInst type outside of the ISAs.
4772:f08370a81812 Fri Jul 27 01:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix argument register indexing.
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.
/gem5/src/base/loader/
H A Dsymtab.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/base/
H A Dsocket.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/sim/
H A Ddvfs_handler.cc10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dsemaphores.py12390:464513ab8668 Wed Dec 13 04:03:00 EST 2017 Gabe Black <gabeblack@google.com> x86: Use operand size 4 when it would be 2 for cmpxchg8b.

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/riscv/
H A Ddecoder.cc12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs

This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.

[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]

Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
/gem5/src/arch/sparc/
H A Dmmapped_ipr.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dremote_gdb.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
3571:ced6d2818217 Wed Nov 08 02:13:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Changed the getReg and setReg functions so that they work like netbsd. Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented.
/gem5/src/arch/
H A Dmicro_asm.py4591:f275f155962a Tue Jun 19 13:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make an error message a little more descriptive.

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