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| H A D | miscregs.hh | 12801:51f4f0331c9d Wed Jun 27 04:35:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Fix incorrect t{0,1}sz field in TTBCR The t0sz and t1sz fields in TTBCR only are only three bits wide unlike aarch64 which has a 6-bit wide field. The higher bits of the aarch64-equivalent should be treated as RES0. Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11589 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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