Searched hist:12505 (Results 1 - 1 of 1) sorted by relevance
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | data64.isa | 12505:1a856c74ec3a Tue Dec 19 16:49:00 EST 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm: Turn dc ivac to dc civac when some conditions are met The Arm ARM defines that at EL1 a data cache invalidate instruction performs a data cache clean and invalidate operation if all of the following apply: * EL2 is implemented, * HCR_EL2.VM is set to 1, * SCR_EL3.NS is set to 1 or EL3 is not implemented. This changeset implements this behavior. Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7826 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
Completed in 7 milliseconds