Searched hist:12448 (Results 1 - 15 of 15) sorted by relevance

/gem5/src/systemc/tests/systemc/kernel/module_method_after_sc_start/
H A Dexpected_returncode13136:f0337b2cd1ca Thu Aug 30 04:43:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Tell verify.py to expect two tests to fail.

These tests purposefully fail when they run, so a return code of 1
should be considered successful.

Change-Id: Ia4ef0469ed946d26a767805ca2d0acd734f1aec9
Reviewed-on: https://gem5-review.googlesource.com/c/12448
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/module_thread_after_sc_start/
H A Dexpected_returncode13136:f0337b2cd1ca Thu Aug 30 04:43:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Tell verify.py to expect two tests to fail.

These tests purposefully fail when they run, so a return code of 1
should be considered successful.

Change-Id: Ia4ef0469ed946d26a767805ca2d0acd734f1aec9
Reviewed-on: https://gem5-review.googlesource.com/c/12448
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/mem/
H A Dse_translating_port_proxy.hh12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dmulti_level_page_table.hh12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dpage_table.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dpage_table.hh12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/riscv/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/arm/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/power/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/alpha/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/mips/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/x86/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/sparc/
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/sim/
H A Dprocess.hh12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dprocess.cc12448:b299e560f1d8 Thu Jan 04 04:22:00 EST 2018 Gabe Black <gabeblack@google.com> arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

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