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/gem5/src/arch/x86/isa/microops/
H A Dmicroops.isa5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5425:4226f6c2d03c Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops which panic, fatal, warn, and warn_once.
/gem5/src/dev/alpha/
H A Dbackdoor.hh11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
H A Dtsunami_cchip.hh11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
/gem5/src/dev/arm/
H A Damba_device.hh7587:177151a54462 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Change how the AMBA device ID checking is done to make it more generic
7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux
/gem5/src/dev/x86/
H A Dspeaker.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/
H A Dsimout11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/
H A Dsimout11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/src/arch/mips/
H A Dsystem.cc9292:e57c7d9736a5 Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Checkpoint: Make system serialize call children

This patch changes how the serialization of the system works. The base
class had a non-virtual serialize and unserialize, that was hidden by
a function with the same name for a number of subclasses (most likely
not intentional as the base class should have been virtual). A few of
the derived systems had no specialization at all (e.g. Power and x86
that simply called the System::serialize), but MIPS and Alpha adds
additional symbol table entries to the checkpoint.

Instead of overriding the virtual function, the additional entries are
now printed through a virtual function (un)serializeSymtab. The reason
for not calling System::serialize from the two related systems is that
a follow up patch will require the system to also serialize the
PhysicalMemory, and if this is done in the base class if ends up being
between the general parts and the specialized symbol table.

With this patch, the checkpoint is not modified, as the order of the
segments is unchanged.
7580:6f77f379a594 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> Loader: Make the load address mask be a parameter of the system rather than a constant.

This allows one two different OS requirements for the same ISA to be handled.
Some OSes are compiled for a virtual address and need to be loaded into physical
memory that starts at address 0, while other bare metal tools generate
images that start at address 0.
/gem5/src/arch/x86/
H A Dpagetable.cc8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
H A Dtypes.cc10924:d02e9c239892 Fri Jul 17 12:31:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> x86: decode instructions with vex prefix

This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
7624:3f32191bcf66 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.
H A Demulenv.cc5966:833e487aa8f7 Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Respect segment override prefixes even when there's no ModRM byte.
4863:b6dacc9a39ff Sat Aug 04 23:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
H A Dvtophys.cc8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/
H A Dconfig.json11951:fbc62d4732be Tue Apr 04 05:44:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the solaris boot stats for the default snoop_filter.

The snoop_filter was enabled by default by this change:

commit 080d4e08d627b5b726afec71d38370373b7376c5
Author: Andreas Hansson <andreas.hansson@arm.com>
Date: Fri Aug 12 14:11:45 2016 +0100

mem: Add snoop filter to SystemXBar by default

Change-Id: I850473c70437588b47812f1dc00d6ecdb66daa36
Reviewed-on: https://gem5-review.googlesource.com/2647
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
10222:d51e31eef415 Mon May 12 17:22:00 EDT 2014 Steve Reinhardt <stever@gmail.com> tests: update t1000 & pc-switcheroo-full stats

committed reference config.json files too
/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
/gem5/src/arch/x86/insts/
H A Dmicroregop.hh7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter.

This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
/gem5/src/arch/x86/isa/formats/
H A Dformats.isa5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
4343:3f11bcf873b3 Fri Apr 06 12:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
H A Dcpuid.isa7622:b49144029ec8 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Mark serializing macroops and regular instructions as such.
5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
/gem5/src/dev/virtio/
H A Dfs9p.hh11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
/gem5/src/base/vnc/
H A Dvncserver.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
9330:4a3269a11230 Fri Nov 02 12:32:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> base: split out the VncServer into a VncInput and Server classes

This patch adds a VncInput base class which VncServer inherits from.
Another class can implement the same interface and be used instead
of the VncServer, for example a class that replays Vnc traffic.
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/
H A Dstats.txt11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes

Completed in 108 milliseconds

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