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/gem5/src/cpu/o3/
H A DO3CPU.py11780:9af039ea0c1e Wed Dec 21 16:04:00 EST 2016 Arthur Perais <arthur.perais@inria.fr> cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3

cachePorts currently constrains the number of store packets written to the
D-Cache each cycle), but loads currently affect this variable. This leads
to unexpected congestion (e.g., setting cachePorts to a realistic 1 will
in fact allow a store to WB only if no loads have accessed the D-Cache
this cycle). In the absence of arbitration, this patch decouples how many
loads can be done per cycle from how many stores can be done per cycle.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
H A Dlsq_unit.hh11780:9af039ea0c1e Wed Dec 21 16:04:00 EST 2016 Arthur Perais <arthur.perais@inria.fr> cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3

cachePorts currently constrains the number of store packets written to the
D-Cache each cycle), but loads currently affect this variable. This leads
to unexpected congestion (e.g., setting cachePorts to a realistic 1 will
in fact allow a store to WB only if no loads have accessed the D-Cache
this cycle). In the absence of arbitration, this patch decouples how many
loads can be done per cycle from how many stores can be done per cycle.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
H A Dlsq_unit_impl.hh11780:9af039ea0c1e Wed Dec 21 16:04:00 EST 2016 Arthur Perais <arthur.perais@inria.fr> cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3

cachePorts currently constrains the number of store packets written to the
D-Cache each cycle), but loads currently affect this variable. This leads
to unexpected congestion (e.g., setting cachePorts to a realistic 1 will
in fact allow a store to WB only if no loads have accessed the D-Cache
this cycle). In the absence of arbitration, this patch decouples how many
loads can be done per cycle from how many stores can be done per cycle.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

Completed in 69 milliseconds