Searched hist:11095 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/mem/slicc/symbols/
H A DVar.py11095:12c36d719139 Mon Sep 14 11:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove member buffer_expr from Var class
This was added by changeset 51f40b101a56. Instead, buffer_expr would now be
associated with the InPort class.
H A DStateMachine.py11095:12c36d719139 Mon Sep 14 11:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove member buffer_expr from Var class
This was added by changeset 51f40b101a56. Instead, buffer_expr would now be
associated with the InPort class.
/gem5/src/mem/slicc/ast/
H A DInPortDeclAST.py11095:12c36d719139 Mon Sep 14 11:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove member buffer_expr from Var class
This was added by changeset 51f40b101a56. Instead, buffer_expr would now be
associated with the InPort class.
/gem5/src/arch/arm/
H A Dstage2_mmu.cc12755:6a5e6dc2824b Wed Jun 13 04:33:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix missing Request allocation

This patch is fixing a missing allocation for a Request buffer
in the Stage2Translation class.

Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11095
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

Completed in 41 milliseconds