Searched hist:10505 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | stage2_lookup.cc | 12734:eb97b1a80c5c Wed May 16 10:27:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Fix page size handling when merging stage 1 and 2 The current code to merge translation entries from stage 1 and stage 2 doesn't handle cases where the page sizes at the different stages differ. This change fixes both the case when the hypervisor has a larger page size and when it has a smaller page size. Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10505 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| /gem5/src/cpu/checker/ | ||
| H A D | cpu.cc | 10505:38c7a9ea7729 Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> cpu: Add support to checker for CACHE_BLOCK_ZERO commands. The checker didn't know how to properly validate these new commands. |
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