Searched defs:CSR_SCAUSE (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | registers.hh | 320 CSR_SCAUSE = 0x142, enumerator in enum:RiscvISA::CSRIndex |
| /gem5/tests/test-progs/asmtest/src/riscv/env/ | ||
| H A D | encoding.h | 792 #define CSR_SCAUSE 0x142 macro |
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