Searched defs:CSR_MHPMEVENT12 (Results 1 - 2 of 2) sorted by relevance
/gem5/src/arch/riscv/ | ||
H A D | registers.hh | 402 CSR_MHPMEVENT12 = 0x32C, enumerator in enum:RiscvISA::CSRIndex |
/gem5/tests/test-progs/asmtest/src/riscv/env/ | ||
H A D | encoding.h | 875 #define CSR_MHPMEVENT12 0x32c macro |
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