Searched defs:CSR_MHPMEVENT10 (Results 1 - 2 of 2) sorted by relevance
/gem5/src/arch/riscv/ | ||
H A D | registers.hh | 400 CSR_MHPMEVENT10 = 0x32A, enumerator in enum:RiscvISA::CSRIndex |
/gem5/tests/test-progs/asmtest/src/riscv/env/ | ||
H A D | encoding.h | 873 #define CSR_MHPMEVENT10 0x32a macro |
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