Searched defs:CLK (Results 76 - 100 of 451) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/
H A Dstimulus.h51 stimulus(sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal<int>& OUT_STIMULUS1, sc_signal_bool_vector& OUT_STIMULUS2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/
H A Ddisplay.h53 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector4& IN_DATA1, const sc_signal_bool_vector5& IN_DATA2, const sc_signal_bool_vector6& IN_DATA3, const sc_signal_bool_vector7& IN_DATA4, const sc_signal_bool_vector8& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/
H A Ddisplay.h57 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector2& IN_VALUE1, const sc_signal_bool_vector2& IN_VALUE2, const sc_signal_bool_vector3& IN_VALUE3, const sc_signal_bool_vector3& IN_VALUE4, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal_bool_vector4& IN_DATA2, const sc_signal_bool_vector4& IN_DATA3, const sc_signal_bool_vector8& IN_DATA4, const sc_signal_bool_vector8& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal_bool_vector4& IN_DATA2, const sc_signal_bool_vector4& IN_DATA3, const sc_signal_bool_vector8& IN_DATA4, const sc_signal_bool_vector8& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal_bool_vector4& IN_DATA2, const sc_signal_bool_vector4& IN_DATA3, const sc_signal_bool_vector8& IN_DATA4, const sc_signal_bool_vector8& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/
H A Ddisplay.h57 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector2& IN_VALUE1, const sc_signal_bool_vector4& IN_VALUE2, const sc_signal_bool_vector6& IN_VALUE3, const sc_signal_bool_vector8& IN_VALUE4, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/
H A Dstimulus.h57 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal<int>& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/
H A Ddisplay.h58 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector4& IN_VALUE1, const sc_signal_bool_vector5& IN_VALUE2, const sc_signal_bool_vector6& IN_VALUE3, const sc_signal_bool_vector7& IN_VALUE4, const sc_signal_bool_vector8& IN_VALUE5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal_bool_vector4& IN_DATA2, const sc_signal_bool_vector4& IN_DATA3, const sc_signal_bool_vector8& IN_DATA4, const sc_signal_bool_vector8& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal<unsigned int>& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal_bool_vector& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal<unsigned int>& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal_bool_vector& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal<unsigned int>& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal_bool_vector& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal<int>& IN_DATA1, const sc_signal<unsigned int>& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal_bool_vector& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector& IN_DATA1, const sc_signal_bool_vector& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal<bool>& IN_VALID1, const sc_signal<bool>& IN_VALID2, const sc_signal<bool>& IN_VALID3 ) argument
H A Dstimulus.h53 stimulus(sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& STIM1, sc_signal_bool_vector& STIM2, sc_signal_bool_vector& STIM3, sc_signal<bool>& INPUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/
H A Ddisplay.h53 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector& IN_DATA1, const sc_signal_bool_vector& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal<bool>& IN_VALID ) argument
H A Dstimulus.h54 stimulus(sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& STIM1, sc_signal_bool_vector& STIM2, sc_signal_bool_vector& STIM3, sc_signal_bool_vector& STIM4, sc_signal<bool>& INPUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector& IN_DATA1, const sc_signal_bool_vector& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal<bool>& IN_VALID1, const sc_signal<bool>& IN_VALID2, const sc_signal<bool>& IN_VALID3 ) argument
H A Dstimulus.h53 stimulus(sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& STIM1, sc_signal_bool_vector& STIM2, sc_signal_bool_vector& STIM3, sc_signal<bool>& INPUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/
H A Dstimulus.h54 stimulus(sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& STIM1, sc_signal_bool_vector& STIM2, sc_signal_bool_vector& STIM3, sc_signal_bool_vector& STIM4, sc_signal<bool>& INPUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector& IN_DATA1, const sc_signal_bool_vector& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal<bool>& IN_VALID1, const sc_signal<bool>& IN_VALID2, const sc_signal<bool>& IN_VALID3 ) argument
H A Dstimulus.h53 stimulus(sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& STIM1, sc_signal_bool_vector& STIM2, sc_signal_bool_vector& STIM3, sc_signal<bool>& INPUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/
H A Ddisplay.h54 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector& IN_DATA1, const sc_signal_bool_vector& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal<int>& IN_DATA5, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/
H A Ddisplay.h53 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector& IN_DATA1, const sc_signal_bool_vector& IN_DATA2, const sc_signal_bool_vector& IN_DATA3, const sc_signal_bool_vector& IN_DATA4, const sc_signal<bool>& IN_VALID ) argument

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