# Copyright (c) 2012 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual # property including but not limited to intellectual property relating # to a hardware implementation of the functionality of the software # licensed hereunder. You may use the software subject to the license # terms below provided that you ensure that this notice is replicated # unmodified and in its entirety in all distributions of the software, # modified or unmodified, in source code or in binary form. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer; # redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution; # neither the name of the copyright holders nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Author: Dam Sunwoo # # Sample stats config file (O3CPU) for m5stats2streamline.py # # Stats grouped together will show as grouped in Streamline. # E.g., # # icache = # icache.overall_hits::total # icache.overall_misses::total # # will display the icache as a stacked line chart. # Charts will still be configurable in Streamline. [PER_CPU_STATS] # "system.cpu#." will automatically prepended for per-CPU stats icache = icache.overall_hits::total icache.overall_misses::total dcache = dcache.overall_hits::total dcache.overall_misses::total [PER_SWITCHCPU_STATS] # If starting from checkpoints, CPU stats will be kept in system.switch_cpus#. # structures. # "system.switch_cpus#" will automatically prepended for per-CPU stats. # Note: L1 caches and table walker caches will still be connected to # system.cpu#! commit_inst_count = commit.committedInsts commit.commitSquashedInsts cycles = numCycles idleCycles branch_mispredict = commit.branchMispredicts itb = itb.hits itb.misses dtb = dtb.hits dtb.misses commit_inst_breakdown = commit.loads commit.membars commit.branches commit.fp_insts commit.int_insts int_regfile = int_regfile_reads int_regfile_writes misc_regfile = misc_regfile_reads misc_regfile_writes rename_full = rename.ROBFullEvents rename.IQFullEvents rename.LSQFullEvents [PER_L2_STATS] # Automatically adapts to how many l2 caches are in the system l2 = overall_hits::total overall_misses::total [OTHER_STATS] # Anything that doesn't belong to CPU or L2 caches physmem = system.physmem.bytes_read::total system.physmem.bytes_written::total