---------- Begin Simulation Statistics ---------- sim_seconds 0.054141 sim_ticks 54141000500 final_tick 54141000500 sim_freq 1000000000000 host_inst_rate 903691 host_op_rate 908191 host_tick_rate 540015581 host_mem_usage 404604 host_seconds 100.26 sim_insts 90602408 sim_ops 91053639 system.voltage_domain.voltage 1 system.clk_domain.clock 1000 system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 system.physmem.bytes_read::cpu.inst 431323084 system.physmem.bytes_read::cpu.data 90016598 system.physmem.bytes_read::total 521339682 system.physmem.bytes_inst_read::cpu.inst 431323084 system.physmem.bytes_inst_read::total 431323084 system.physmem.bytes_written::cpu.data 18908138 system.physmem.bytes_written::total 18908138 system.physmem.num_reads::cpu.inst 107830771 system.physmem.num_reads::cpu.data 22461532 system.physmem.num_reads::total 130292303 system.physmem.num_writes::cpu.data 4738868 system.physmem.num_writes::total 4738868 system.physmem.bw_read::cpu.inst 7966662604 system.physmem.bw_read::cpu.data 1662632703 system.physmem.bw_read::total 9629295306 system.physmem.bw_inst_read::cpu.inst 7966662604 system.physmem.bw_inst_read::total 7966662604 system.physmem.bw_write::cpu.data 349238799 system.physmem.bw_write::total 349238799 system.physmem.bw_total::cpu.inst 7966662604 system.physmem.bw_total::cpu.data 2011871502 system.physmem.bw_total::total 9978534106 system.pwrStateResidencyTicks::UNDEFINED 54141000500 system.cpu_clk_domain.clock 500 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 system.cpu.dstage2_mmu.stage2_tlb.misses 0 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 system.cpu.dtb.walker.walks 0 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 system.cpu.dtb.walker.walkRequestOrigin::total 0 system.cpu.dtb.inst_hits 0 system.cpu.dtb.inst_misses 0 system.cpu.dtb.read_hits 0 system.cpu.dtb.read_misses 0 system.cpu.dtb.write_hits 0 system.cpu.dtb.write_misses 0 system.cpu.dtb.flush_tlb 0 system.cpu.dtb.flush_tlb_mva 0 system.cpu.dtb.flush_tlb_mva_asid 0 system.cpu.dtb.flush_tlb_asid 0 system.cpu.dtb.flush_entries 0 system.cpu.dtb.align_faults 0 system.cpu.dtb.prefetch_faults 0 system.cpu.dtb.domain_faults 0 system.cpu.dtb.perms_faults 0 system.cpu.dtb.read_accesses 0 system.cpu.dtb.write_accesses 0 system.cpu.dtb.inst_accesses 0 system.cpu.dtb.hits 0 system.cpu.dtb.misses 0 system.cpu.dtb.accesses 0 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 system.cpu.istage2_mmu.stage2_tlb.misses 0 system.cpu.istage2_mmu.stage2_tlb.accesses 0 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 system.cpu.itb.walker.walks 0 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 system.cpu.itb.walker.walkRequestOrigin::total 0 system.cpu.itb.inst_hits 0 system.cpu.itb.inst_misses 0 system.cpu.itb.read_hits 0 system.cpu.itb.read_misses 0 system.cpu.itb.write_hits 0 system.cpu.itb.write_misses 0 system.cpu.itb.flush_tlb 0 system.cpu.itb.flush_tlb_mva 0 system.cpu.itb.flush_tlb_mva_asid 0 system.cpu.itb.flush_tlb_asid 0 system.cpu.itb.flush_entries 0 system.cpu.itb.align_faults 0 system.cpu.itb.prefetch_faults 0 system.cpu.itb.domain_faults 0 system.cpu.itb.perms_faults 0 system.cpu.itb.read_accesses 0 system.cpu.itb.write_accesses 0 system.cpu.itb.inst_accesses 0 system.cpu.itb.hits 0 system.cpu.itb.misses 0 system.cpu.itb.accesses 0 system.cpu.workload.numSyscalls 442 system.cpu.pwrStateResidencyTicks::ON 54141000500 system.cpu.numCycles 108282002 system.cpu.numWorkItemsStarted 0 system.cpu.numWorkItemsCompleted 0 system.cpu.committedInsts 90602408 system.cpu.committedOps 91053639 system.cpu.num_int_alu_accesses 72326352 system.cpu.num_fp_alu_accesses 48 system.cpu.num_func_calls 112245 system.cpu.num_conditional_control_insts 15520157 system.cpu.num_int_insts 72326352 system.cpu.num_fp_insts 48 system.cpu.num_int_register_reads 124257600 system.cpu.num_int_register_writes 52782988 system.cpu.num_fp_register_reads 54 system.cpu.num_fp_register_writes 30 system.cpu.num_cc_register_reads 271814243 system.cpu.num_cc_register_writes 53956115 system.cpu.num_mem_refs 27220755 system.cpu.num_load_insts 22475911 system.cpu.num_store_insts 4744844 system.cpu.num_idle_cycles 0 system.cpu.num_busy_cycles 108282002 system.cpu.not_idle_fraction 1 system.cpu.idle_fraction 0 system.cpu.Branches 18732305 system.cpu.op_class::No_OpClass 0 0.00% 0.00% system.cpu.op_class::IntAlu 63822829 70.09% 70.09% system.cpu.op_class::IntMult 10474 0.01% 70.10% system.cpu.op_class::IntDiv 0 0.00% 70.10% system.cpu.op_class::FloatAdd 0 0.00% 70.10% system.cpu.op_class::FloatCmp 0 0.00% 70.10% system.cpu.op_class::FloatCvt 0 0.00% 70.10% system.cpu.op_class::FloatMult 0 0.00% 70.10% system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% system.cpu.op_class::FloatDiv 0 0.00% 70.10% system.cpu.op_class::FloatMisc 0 0.00% 70.10% system.cpu.op_class::FloatSqrt 0 0.00% 70.10% system.cpu.op_class::SimdAdd 0 0.00% 70.10% system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% system.cpu.op_class::SimdAlu 0 0.00% 70.10% system.cpu.op_class::SimdCmp 0 0.00% 70.10% system.cpu.op_class::SimdCvt 0 0.00% 70.10% system.cpu.op_class::SimdMisc 0 0.00% 70.10% system.cpu.op_class::SimdMult 0 0.00% 70.10% system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% system.cpu.op_class::SimdShift 0 0.00% 70.10% system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% system.cpu.op_class::SimdSqrt 0 0.00% 70.10% system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% system.cpu.op_class::MemRead 22475905 24.68% 94.79% system.cpu.op_class::MemWrite 4744822 5.21% 100.00% system.cpu.op_class::FloatMemRead 6 0.00% 100.00% system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% system.cpu.op_class::IprAccess 0 0.00% 100.00% system.cpu.op_class::InstPrefetch 0 0.00% 100.00% system.cpu.op_class::total 91054081 system.membus.snoop_filter.tot_requests 0 system.membus.snoop_filter.hit_single_requests 0 system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 system.membus.snoop_filter.hit_single_snoops 0 system.membus.snoop_filter.hit_multi_snoops 0 system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 system.membus.trans_dist::ReadReq 130287906 system.membus.trans_dist::ReadResp 130291793 system.membus.trans_dist::WriteReq 4734981 system.membus.trans_dist::WriteResp 4734981 system.membus.trans_dist::SoftPFReq 510 system.membus.trans_dist::SoftPFResp 510 system.membus.trans_dist::LoadLockedReq 3887 system.membus.trans_dist::StoreCondReq 3887 system.membus.trans_dist::StoreCondResp 3887 system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 system.membus.pkt_count::total 270062342 system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 system.membus.pkt_size::total 540247820 system.membus.snoops 0 system.membus.snoopTraffic 0 system.membus.snoop_fanout::samples 135031171 system.membus.snoop_fanout::mean 0 system.membus.snoop_fanout::stdev 0 system.membus.snoop_fanout::underflows 0 0.00% 0.00% system.membus.snoop_fanout::0 135031171 100.00% 100.00% system.membus.snoop_fanout::1 0 0.00% 100.00% system.membus.snoop_fanout::overflows 0 0.00% 100.00% system.membus.snoop_fanout::min_value 0 system.membus.snoop_fanout::max_value 0 system.membus.snoop_fanout::total 135031171 ---------- End Simulation Statistics ----------