---------- Begin Simulation Statistics ---------- sim_seconds 0.058768 # Number of seconds simulated sim_ticks 58768125500 # Number of ticks simulated final_tick 58768125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 140139 # Simulator instruction rate (inst/s) host_op_rate 179217 # Simulator op (including micro ops) rate (op/s) host_tick_rate 116134728 # Simulator tick rate (ticks/s) host_mem_usage 275656 # Number of bytes of host memory used host_seconds 506.03 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 285632 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory system.physmem.bytes_read::total 8210304 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 285632 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 285632 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5517568 # Number of bytes written to this memory system.physmem.bytes_written::total 5517568 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4463 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory system.physmem.num_reads::total 128286 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86212 # Number of write requests responded to by this memory system.physmem.num_writes::total 86212 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 4860322 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 134846431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 139706753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 4860322 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 4860322 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 93887085 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 93887085 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 93887085 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 4860322 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 134846431 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 233593838 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128286 # Number of read requests accepted system.physmem.writeReqs 86212 # Number of write requests accepted system.physmem.readBursts 128286 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86212 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8209920 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue system.physmem.bytesWritten 5515840 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8210304 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5517568 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8065 # Per bank write bursts system.physmem.perBankRdBursts::1 8314 # Per bank write bursts system.physmem.perBankRdBursts::2 8239 # Per bank write bursts system.physmem.perBankRdBursts::3 8142 # Per bank write bursts system.physmem.perBankRdBursts::4 8284 # Per bank write bursts system.physmem.perBankRdBursts::5 8404 # Per bank write bursts system.physmem.perBankRdBursts::6 8054 # Per bank write bursts system.physmem.perBankRdBursts::7 7915 # Per bank write bursts system.physmem.perBankRdBursts::8 8035 # Per bank write bursts system.physmem.perBankRdBursts::9 7585 # Per bank write bursts system.physmem.perBankRdBursts::10 7763 # Per bank write bursts system.physmem.perBankRdBursts::11 7814 # Per bank write bursts system.physmem.perBankRdBursts::12 7871 # Per bank write bursts system.physmem.perBankRdBursts::13 7866 # Per bank write bursts system.physmem.perBankRdBursts::14 7967 # Per bank write bursts system.physmem.perBankRdBursts::15 7962 # Per bank write bursts system.physmem.perBankWrBursts::0 5395 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts system.physmem.perBankWrBursts::2 5468 # Per bank write bursts system.physmem.perBankWrBursts::3 5336 # Per bank write bursts system.physmem.perBankWrBursts::4 5363 # Per bank write bursts system.physmem.perBankWrBursts::5 5561 # Per bank write bursts system.physmem.perBankWrBursts::6 5259 # Per bank write bursts system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5154 # Per bank write bursts system.physmem.perBankWrBursts::9 5103 # Per bank write bursts system.physmem.perBankWrBursts::10 5293 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts system.physmem.perBankWrBursts::14 5703 # Per bank write bursts system.physmem.perBankWrBursts::15 5431 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 58768094000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 128286 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86212 # Write request sizes (log2) system.physmem.rdQLenPdf::0 116156 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4059 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5319 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5316 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5334 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5514 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5445 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5466 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5870 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5486 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 353.665026 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 214.783131 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 335.990632 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12260 31.60% 31.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 8290 21.36% 52.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4146 10.68% 63.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2807 7.23% 70.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2540 6.55% 77.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1701 4.38% 81.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1262 3.25% 85.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1176 3.03% 88.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4621 11.91% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 24.212911 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 352.385643 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5295 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.269398 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.253066 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.759205 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 4663 88.03% 88.03% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 7 0.13% 88.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 496 9.36% 97.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 16 0.30% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 8 0.15% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads system.physmem.totQLat 1679255750 # Total ticks spent queuing system.physmem.totMemAccLat 4084505750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 641400000 # Total ticks spent in databus transfers system.physmem.avgQLat 13090.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 31840.55 # Average memory access latency per DRAM burst system.physmem.avgRdBW 139.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 93.86 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 139.71 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 93.89 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.82 # Data bus utilization in percentage system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing system.physmem.readRowHits 111800 # Number of row buffer hits during reads system.physmem.writeRowHits 63851 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.06 # Row buffer hit rate for writes system.physmem.avgGap 273979.68 # Average gap between requests system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 153014400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 83490000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 509886000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 279190800 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 11659704255 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 25030042500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 41553430275 # Total energy per rank (pJ) system.physmem_0.averagePower 707.134890 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 41510709500 # Time in different power states system.physmem_0.memoryStateTime::REF 1962220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15290173000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 140215320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 76506375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 490152000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279145440 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 11133864720 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 25491305250 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 41449291425 # Total energy per rank (pJ) system.physmem_1.averagePower 705.362708 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 42280803500 # Time in different power states system.physmem_1.memoryStateTime::REF 1962220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14520166000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14827521 # Number of BP lookups system.cpu.branchPred.condPredicted 9922528 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 342114 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 9663077 # Number of BTB lookups system.cpu.branchPred.BTBHits 6571727 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 68.008637 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1719937 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 176106 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 158425 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 17681 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24889 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.pwrStateResidencyTicks::ON 58768125500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 117536251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed system.cpu.discardedOps 1179302 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.657421 # CPI: cycles per instruction system.cpu.ipc 0.603347 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction system.cpu.tickCycles 97988256 # Number of cycles that the object actually ticked system.cpu.idleCycles 19547995 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156444 # number of replacements system.cpu.dcache.tags.tagsinuse 4068.129500 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42637241 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160540 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 265.586402 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 821026500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4068.129500 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993196 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993196 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1100 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2952 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86035236 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86035236 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22879875 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22879875 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642158 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642158 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83370 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 83370 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 42522033 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 42522033 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 42605403 # number of overall hits system.cpu.dcache.overall_hits::total 42605403 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 47768 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 47768 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207743 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 207743 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 44596 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 44596 # number of SoftPFReq misses system.cpu.dcache.demand_misses::cpu.data 255511 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 255511 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 300107 # number of overall misses system.cpu.dcache.overall_misses::total 300107 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 1443300500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 1443300500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 16810663000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 16810663000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 18253963500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 18253963500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 18253963500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 18253963500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22927643 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22927643 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 127966 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 127966 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 42777544 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42777544 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42905510 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42905510 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002083 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002083 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348499 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.348499 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.005973 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.005973 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006995 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006995 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30214.798610 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 30214.798610 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80920.478668 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80920.478668 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 71441.008411 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 71441.008411 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 60824.850803 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 60824.850803 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 128383 # number of writebacks system.cpu.dcache.writebacks::total 128383 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18246 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 18246 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100706 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 100706 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 118952 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 118952 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 118952 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 118952 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29522 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29522 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 136559 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 136559 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160540 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160540 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 576668000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 576668000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488003000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488003000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1709526500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1709526500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9064671000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9064671000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10774197500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10774197500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187401 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187401 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19533.500440 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19533.500440 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79299.709446 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79299.709446 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71286.706142 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71286.706142 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66379.154798 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66379.154798 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67112.230597 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67112.230597 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43538 # number of replacements system.cpu.icache.tags.tagsinuse 1854.967198 # Cycle average of tags in use system.cpu.icache.tags.total_refs 25047260 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 45580 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 549.523036 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1854.967198 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.905746 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.905746 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 907 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1012 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50231262 # Number of tag accesses system.cpu.icache.tags.data_accesses 50231262 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 25047260 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25047260 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25047260 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 25047260 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 25047260 # number of overall hits system.cpu.icache.overall_hits::total 25047260 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 45581 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 45581 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 45581 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 45581 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 45581 # number of overall misses system.cpu.icache.overall_misses::total 45581 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 906370500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 906370500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 906370500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 906370500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 906370500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 906370500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25092841 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25092841 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25092841 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 25092841 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 25092841 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25092841 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001816 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001816 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001816 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001816 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001816 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001816 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19884.831399 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 19884.831399 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 19884.831399 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 19884.831399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 43538 # number of writebacks system.cpu.icache.writebacks::total 43538 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45581 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 45581 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 45581 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 45581 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 45581 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 45581 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 860790500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 860790500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 860790500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 860790500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 860790500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 860790500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001816 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001816 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001816 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18884.853338 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18884.853338 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96393 # number of replacements system.cpu.l2cache.tags.tagsinuse 29915.680999 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 163475 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127546 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.281694 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26835.960013 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1436.225853 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1643.495133 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.818969 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043830 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.050155 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.912954 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15761 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 596 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3420655 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3420655 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128383 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128383 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39935 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 39935 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4757 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4757 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41105 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 41105 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31900 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 31900 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 41105 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36657 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 77762 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 41105 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36657 # number of overall hits system.cpu.l2cache.overall_hits::total 77762 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4476 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 4476 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 4476 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 123883 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 128359 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 4476 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123883 # number of overall misses system.cpu.l2cache.overall_misses::total 128359 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277452000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8277452000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356943000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 356943000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1866770000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1866770000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 356943000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10144222000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10501165000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 356943000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10144222000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10501165000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 128383 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 128383 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 39935 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 39935 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45581 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 45581 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 45581 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 160540 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 206121 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 45581 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 160540 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 206121 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955557 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955557 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098199 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098199 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403772 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403772 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098199 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.622736 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098199 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.622736 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80929.331248 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80929.331248 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79745.978552 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79745.978552 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86412.535296 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86412.535296 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79745.978552 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81885.504872 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 81810.897561 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79745.978552 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81885.504872 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 81810.897561 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 86212 # number of writebacks system.cpu.l2cache.writebacks::total 86212 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4464 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4464 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21543 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21543 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 4464 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128287 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 4464 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128287 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7254652000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7254652000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 311353500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 311353500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1646809500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1646809500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 311353500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8901461500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 9212815000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311353500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8901461500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 9212815000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955557 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955557 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097936 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402650 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402650 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.622387 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.622387 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70929.331248 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70929.331248 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69747.647849 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69747.647849 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76442.904888 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76442.904888 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 406103 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 200020 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99083 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43538 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 38242 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 45581 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477524 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 612223 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5703552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24194624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 96393 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5517568 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 302514 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.037258 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.189899 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 291272 96.28% 96.28% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 11213 3.71% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 302514 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 374972500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 68384970 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240842435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26006 # Transaction distribution system.membus.trans_dist::WritebackDirty 86212 # Transaction distribution system.membus.trans_dist::CleanEvict 6916 # Transaction distribution system.membus.trans_dist::ReadExReq 102280 # Transaction distribution system.membus.trans_dist::ReadExResp 102280 # Transaction distribution system.membus.trans_dist::ReadSharedReq 26006 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349700 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 349700 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727872 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13727872 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 221414 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 221414 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 221414 # Request fanout histogram system.membus.reqLayer0.occupancy 586752500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) system.membus.respLayer1.occupancy 676437000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ----------