---------- Begin Simulation Statistics ---------- final_tick 1252658454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 126529 # Simulator instruction rate (inst/s) host_mem_usage 303852 # Number of bytes of host memory used host_op_rate 172315 # Simulator op (including micro ops) rate (op/s) host_seconds 10941.24 # Real time elapsed on the host host_tick_rate 114489637 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1384383018 # Number of instructions simulated sim_ops 1885337770 # Number of ops (including micro ops) simulated sim_seconds 1.252658 # Number of seconds simulated sim_ticks 1252658454500 # Number of ticks simulated system.clk_domain.clock 1000 # Clock period in ticks system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 92.275361 # BTB Hit Percentage system.cpu.branchPred.BTBHits 183176705 # Number of BTB hits system.cpu.branchPred.BTBLookups 198510960 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 2809 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 27775706 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 271023918 # Number of conditional branches predicted system.cpu.branchPred.lookups 347774230 # Number of BP lookups system.cpu.branchPred.usedRAS 40383236 # Number of times the RAS was used to get a target. system.cpu.committedInsts 1384383018 # Number of instructions committed system.cpu.committedOps 1885337770 # Number of ops (including micro ops) committed system.cpu.cpi 1.809699 # CPI: cycles per instruction system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits::cpu.inst 9985 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses::cpu.inst 622157845 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 622157845 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits::cpu.inst 620694666 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 620694666 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44632990969 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 44632990969 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002352 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002352 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses::cpu.inst 1463179 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1463179 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 1721 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1721 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41566397026 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 41566397026 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002349 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002349 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1461458 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1461458 # number of ReadReq MSHR misses system.cpu.dcache.StoreCondReq_accesses::cpu.inst 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits::cpu.inst 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses::cpu.inst 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits::cpu.inst 276792059 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276792059 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9251708000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9251708000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000519 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000519 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses::cpu.inst 143619 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 143619 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70841 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 70841 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4560363750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4560363750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000263 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 72778 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72778 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses::cpu.inst 899093523 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 899093523 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 33535.453099 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency system.cpu.dcache.demand_hits::cpu.inst 897486725 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 897486725 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency::cpu.inst 53884698969 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 53884698969 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate::cpu.inst 0.001787 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.001787 # miss rate for demand accesses system.cpu.dcache.demand_misses::cpu.inst 1606798 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1606798 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits::cpu.inst 72562 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 72562 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 46126760776 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 46126760776 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001706 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses::cpu.inst 1534236 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1534236 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses::cpu.inst 899093523 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 899093523 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33535.453099 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency system.cpu.dcache.overall_hits::cpu.inst 897486725 # number of overall hits system.cpu.dcache.overall_hits::total 897486725 # number of overall hits system.cpu.dcache.overall_miss_latency::cpu.inst 53884698969 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 53884698969 # number of overall miss cycles system.cpu.dcache.overall_miss_rate::cpu.inst 0.001787 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001787 # miss rate for overall accesses system.cpu.dcache.overall_misses::cpu.inst 1606798 # number of overall misses system.cpu.dcache.overall_misses::total 1606798 # number of overall misses system.cpu.dcache.overall_mshr_hits::cpu.inst 72562 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 72562 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 46126760776 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 46126760776 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001706 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses::cpu.inst 1534236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1534236 # number of overall MSHR misses system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1240 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1699 # Occupied blocks per task id system.cpu.dcache.tags.avg_refs 584.986075 # Average number of references to valid blocks. system.cpu.dcache.tags.data_accesses 1799761222 # Number of data accesses system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.531713 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999642 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999642 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.replacements 1530140 # number of replacements system.cpu.dcache.tags.sampled_refs 1534236 # Sample count of references to valid blocks. system.cpu.dcache.tags.tag_accesses 1799761222 # Number of tag accesses system.cpu.dcache.tags.tagsinuse 4094.531713 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 897506695 # Total number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 756574250 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks::writebacks 96100 # number of writebacks system.cpu.dcache.writebacks::total 96100 # number of writebacks system.cpu.discardedOps 58655042 # Number of ops (including micro ops) which were discarded before commit system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses::cpu.inst 655834828 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 655834828 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits::cpu.inst 655779494 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 655779494 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency::cpu.inst 873992996 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 873992996 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses::cpu.inst 55334 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 55334 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 762208004 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 762208004 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 55334 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 55334 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses::cpu.inst 655834828 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 655834828 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 15794.863845 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency system.cpu.icache.demand_hits::cpu.inst 655779494 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 655779494 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency::cpu.inst 873992996 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 873992996 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.icache.demand_misses::cpu.inst 55334 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 55334 # number of demand (read+write) misses system.cpu.icache.demand_mshr_miss_latency::cpu.inst 762208004 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 762208004 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses::cpu.inst 55334 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 55334 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses::cpu.inst 655834828 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 655834828 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 15794.863845 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency system.cpu.icache.overall_hits::cpu.inst 655779494 # number of overall hits system.cpu.icache.overall_hits::total 655779494 # number of overall hits system.cpu.icache.overall_miss_latency::cpu.inst 873992996 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 873992996 # number of overall miss cycles system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses system.cpu.icache.overall_misses::cpu.inst 55334 # number of overall misses system.cpu.icache.overall_misses::total 55334 # number of overall misses system.cpu.icache.overall_mshr_miss_latency::cpu.inst 762208004 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 762208004 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses::cpu.inst 55334 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 55334 # number of overall MSHR misses system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id system.cpu.icache.tags.avg_refs 11851.508033 # Average number of references to valid blocks. system.cpu.icache.tags.data_accesses 1311724989 # Number of data accesses system.cpu.icache.tags.occ_blocks::cpu.inst 1727.262157 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.843390 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.843390 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1765 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.861816 # Percentage of cache occupancy per task id system.cpu.icache.tags.replacements 53568 # number of replacements system.cpu.icache.tags.sampled_refs 55333 # Sample count of references to valid blocks. system.cpu.icache.tags.tag_accesses 1311724989 # Number of tag accesses system.cpu.icache.tags.tagsinuse 1727.262157 # Cycle average of tags in use system.cpu.icache.tags.total_refs 655779494 # Total number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.idleCycles 103571975 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.ipc 0.552578 # IPC: instructions per cycle system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses::cpu.inst 72778 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72778 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits::cpu.inst 6688 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6688 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4420703750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4420703750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.908104 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.908104 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses::cpu.inst 66090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3592273750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3592273750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.908104 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908104 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses::cpu.inst 1516792 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1516792 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72703.861690 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 72703.861690 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60134.219047 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60134.219047 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits::cpu.inst 1107826 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1107826 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29733407500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 29733407500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269626 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.269626 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses::cpu.inst 408966 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 408966 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 30 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24591047000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24591047000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269606 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269606 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 408936 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 408936 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses::writebacks 96100 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 96100 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits::writebacks 96100 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 96100 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses::cpu.inst 1589570 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 1589570 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 71894.916073 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency system.cpu.l2cache.demand_hits::cpu.inst 1114514 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1114514 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency::cpu.inst 34154111250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 34154111250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate::cpu.inst 0.298858 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.298858 # miss rate for demand accesses system.cpu.l2cache.demand_misses::cpu.inst 475056 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 475056 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28183320750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 28183320750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.298839 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses::cpu.inst 475026 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 475026 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses::cpu.inst 1589570 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1589570 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 71894.916073 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency system.cpu.l2cache.overall_hits::cpu.inst 1114514 # number of overall hits system.cpu.l2cache.overall_hits::total 1114514 # number of overall hits system.cpu.l2cache.overall_miss_latency::cpu.inst 34154111250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 34154111250 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate::cpu.inst 0.298858 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.298858 # miss rate for overall accesses system.cpu.l2cache.overall_misses::cpu.inst 475056 # number of overall misses system.cpu.l2cache.overall_misses::total 475056 # number of overall misses system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28183320750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 28183320750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.298839 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses::cpu.inst 475026 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 475026 # number of overall MSHR misses system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2580 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29670 # Occupied blocks per task id system.cpu.l2cache.tags.avg_refs 2.395162 # Average number of references to valid blocks. system.cpu.l2cache.tags.data_accesses 14033128 # Number of data accesses system.cpu.l2cache.tags.occ_blocks::writebacks 1330.818076 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.040613 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956568 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997182 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.replacements 442246 # number of replacements system.cpu.l2cache.tags.sampled_refs 474990 # Sample count of references to valid blocks. system.cpu.l2cache.tags.tag_accesses 14033128 # Number of tag accesses system.cpu.l2cache.tags.tagsinuse 32675.650864 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1137678 # Total number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks system.cpu.numCycles 2505316909 # number of cpu cycles simulated system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.tickCycles 2401744934 # Number of cycles that the CPU actually ticked system.cpu.toL2Bus.data_through_bus 107882816 # Total data (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 110667 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3164572 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3275239 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 938935000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 83558996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2375968224 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.throughput 86123089 # Throughput (bytes/s) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3541312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104341504 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 107882816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.trans_dist::ReadReq 1516792 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1516791 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 96100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72778 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72778 # Transaction distribution system.cpu.workload.num_syscalls 1411 # Number of system calls system.cpu_clk_domain.clock 500 # Clock period in ticks system.membus.data_through_bus 34631936 # Total data (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1016149 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1016149 # Packet count per connected master and slave (bytes) system.membus.reqLayer0.occupancy 1205459500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 4468586250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.throughput 27646751 # Throughput (bytes/s) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34631936 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 34631936 # Cumulative packet size per connected master and slave (bytes) system.membus.trans_dist::ReadReq 408935 # Transaction distribution system.membus.trans_dist::ReadResp 408935 # Transaction distribution system.membus.trans_dist::Writeback 66099 # Transaction distribution system.membus.trans_dist::ReadExReq 66090 # Transaction distribution system.membus.trans_dist::ReadExResp 66090 # Transaction distribution system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgGap 2314919.25 # Average gap between requests system.physmem.avgMemAccLat 29362.18 # Average memory access latency per DRAM burst system.physmem.avgQLat 10612.18 # Average queueing delay per DRAM burst system.physmem.avgRdBW 24.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBWSys 24.27 # Average system read bandwidth in MiByte/s system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBWSys 3.38 # Average system write bandwidth in MiByte/s system.physmem.avgWrQLen 26.46 # Average write queue length when enqueuing system.physmem.busUtil 0.22 # Data bus utilization in percentage system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.bw_inst_read::cpu.inst 133348 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 133348 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 24269664 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 24269664 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3377087 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 24269664 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 27646751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_write::writebacks 3377087 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3377087 # Write bandwidth from this memory (bytes/s) system.physmem.bytesPerActivate::samples 204371 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 169.307779 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 122.893449 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 197.869772 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 84097 41.15% 41.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 91184 44.62% 85.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 16888 8.26% 94.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 803 0.39% 94.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1089 0.53% 94.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1331 0.65% 95.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 576 0.28% 95.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 520 0.25% 96.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7883 3.86% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 204371 # Bytes accessed per row activation system.physmem.bytesReadDRAM 30374976 # Total number of bytes read from DRAM system.physmem.bytesReadSys 30401600 # Total read bytes from the system interface side system.physmem.bytesReadWrQ 26624 # Total number of bytes read from write queue system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM system.physmem.bytesWrittenSys 4230336 # Total written bytes from the system interface side system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory system.physmem.bytes_read::cpu.inst 30401600 # Number of bytes read from this memory system.physmem.bytes_read::total 30401600 # Number of bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory system.physmem.memoryStateTime::IDLE 639262116250 # Time in different power states system.physmem.memoryStateTime::REF 41828800000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 571561257500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.num_reads::cpu.inst 475025 # Number of read requests responded to by this memory system.physmem.num_reads::total 475025 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory system.physmem.pageHitRate 62.20 # Row buffer hit rate, read and write combined system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 29837 # Per bank write bursts system.physmem.perBankRdBursts::1 29647 # Per bank write bursts system.physmem.perBankRdBursts::2 29757 # Per bank write bursts system.physmem.perBankRdBursts::3 29702 # Per bank write bursts system.physmem.perBankRdBursts::4 29776 # Per bank write bursts system.physmem.perBankRdBursts::5 29847 # Per bank write bursts system.physmem.perBankRdBursts::6 29613 # Per bank write bursts system.physmem.perBankRdBursts::7 29430 # Per bank write bursts system.physmem.perBankRdBursts::8 29457 # Per bank write bursts system.physmem.perBankRdBursts::9 29488 # Per bank write bursts system.physmem.perBankRdBursts::10 29541 # Per bank write bursts system.physmem.perBankRdBursts::11 29643 # Per bank write bursts system.physmem.perBankRdBursts::12 29678 # Per bank write bursts system.physmem.perBankRdBursts::13 29796 # Per bank write bursts system.physmem.perBankRdBursts::14 29601 # Per bank write bursts system.physmem.perBankRdBursts::15 29796 # Per bank write bursts system.physmem.perBankWrBursts::0 4173 # Per bank write bursts system.physmem.perBankWrBursts::1 4100 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts system.physmem.perBankWrBursts::8 4094 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts system.physmem.perBankWrBursts::10 4093 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4094 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 36.067006 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 508.980201 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes system.physmem.rdQLenPdf::0 474221 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 373 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.readBursts 475025 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 475025 # Read request sizes (log2) system.physmem.readReqs 475025 # Number of read requests accepted system.physmem.readRowHitRate 60.31 # Row buffer hit rate for reads system.physmem.readRowHits 286253 # Number of row buffer hits during reads system.physmem.servicedByWrQ 416 # Number of DRAM read bursts serviced by the write queue system.physmem.totBusLat 2373045000 # Total ticks spent in databus transfers system.physmem.totGap 1252658366500 # Total gap between requests system.physmem.totMemAccLat 13935557250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totQLat 5036638500 # Total ticks spent queuing system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.489144 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.467620 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.859483 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 3026 75.52% 75.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 2 0.05% 75.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.writeBursts 66099 # Number of DRAM write bursts, including those merged in the write queue system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66099 # Write request sizes (log2) system.physmem.writeReqs 66099 # Number of write requests accepted system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes system.physmem.writeRowHits 50044 # Number of row buffer hits during writes system.voltage_domain.voltage 1 # Voltage in Volts ---------- End Simulation Statistics ----------