---------- Begin Simulation Statistics ---------- sim_seconds 0.458202 # Number of seconds simulated sim_ticks 458201684000 # Number of ticks simulated final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 111882 # Simulator instruction rate (inst/s) host_op_rate 206882 # Simulator op (including micro ops) rate (op/s) host_tick_rate 61997502 # Simulator tick rate (ticks/s) host_mem_usage 341328 # Number of bytes of host memory used host_seconds 7390.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24476096 # Number of bytes read from this memory system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 201408 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 201408 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18788864 # Number of bytes written to this memory system.physmem.bytes_written::total 18788864 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3147 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 382439 # Number of read requests responded to by this memory system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 293576 # Number of write requests responded to by this memory system.physmem.num_writes::total 293576 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 439562 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 53417735 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 53857297 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 439562 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 439562 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 41005663 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 41005663 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 41005663 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 385586 # Total number of read requests seen system.physmem.writeReqs 293576 # Total number of write requests seen system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 24677504 # Total number of bytes read from memory system.physmem.bytesWritten 18788864 # Total number of bytes written to memory system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 24657 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 24489 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 23219 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 23674 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 24391 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 24210 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 23623 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 23844 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 24783 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 24073 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 23240 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 22943 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 23791 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 24001 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 19821 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 18940 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 18905 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 18411 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 18971 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 18943 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 18119 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 18810 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 17724 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 17345 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 16945 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 17717 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 17828 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry system.physmem.totGap 458201657000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 385586 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 293576 # Categorize write packet sizes system.physmem.rdQLenPdf::0 380883 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 4226 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 12723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 12732 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 12740 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 12743 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 12746 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 12748 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 12750 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 12764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 125877 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 345.228437 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 161.863436 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 669.217085 # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 54117 42.99% 42.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-129 23349 18.55% 61.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::192-193 10530 8.37% 69.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-257 6425 5.10% 75.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::320-321 4023 3.20% 78.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-385 2874 2.28% 80.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-449 2162 1.72% 82.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-513 1748 1.39% 83.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-577 1399 1.11% 84.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 1145 0.91% 85.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-705 1227 0.97% 86.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 1117 0.89% 87.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::832-833 747 0.59% 88.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-897 630 0.50% 88.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::960-961 615 0.49% 89.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1025 623 0.49% 89.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 541 0.43% 89.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 508 0.40% 90.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216-1217 588 0.47% 90.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 726 0.58% 91.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344-1345 627 0.50% 91.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 694 0.55% 92.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 6218 4.94% 97.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 497 0.39% 97.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600-1601 336 0.27% 98.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1665 279 0.22% 98.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::1728-1729 216 0.17% 98.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1793 162 0.13% 98.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 151 0.12% 98.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::1920-1921 121 0.10% 98.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 106 0.08% 98.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048-2049 85 0.07% 98.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 80 0.06% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 63 0.05% 99.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 41 0.03% 99.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 42 0.03% 99.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::2432-2433 32 0.03% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 20 0.02% 99.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::2624-2625 25 0.02% 99.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 22 0.02% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::2752-2753 23 0.02% 99.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 14 0.01% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::2944-2945 22 0.02% 99.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 12 0.01% 99.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 19 0.02% 99.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 11 0.01% 99.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::3200-3201 20 0.02% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 17 0.01% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3329 11 0.01% 99.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::3392-3393 14 0.01% 99.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3457 8 0.01% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 8 0.01% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3713 7 0.01% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::3840-3841 14 0.01% 99.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3905 8 0.01% 99.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::4224-4225 3 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4289 6 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4353 5 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480-4481 3 0.00% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4545 5 0.00% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4673 9 0.01% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 9 0.01% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928-4929 4 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::4992-4993 4 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5121 3 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::5184-5185 4 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5377 4 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5505 8 0.01% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5697 5 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 3 0.00% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6657 10 0.01% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 5 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 4 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 4 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7936-7937 4 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 377 0.30% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 125877 # Bytes accessed per row activation system.physmem.totQLat 3046093750 # Total cycles spent in queuing delays system.physmem.totMemAccLat 11221540000 # Sum of mem lat for all requests system.physmem.totBusLat 1927185000 # Total cycles spent in databus access system.physmem.totBankLat 6248261250 # Total cycles spent in bank access system.physmem.avgQLat 7902.96 # Average queueing delay per request system.physmem.avgBankLat 16210.85 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29113.81 # Average memory access latency system.physmem.avgRdBW 53.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.86 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time system.physmem.avgWrQLen 9.78 # Average write queue length over time system.physmem.readRowHits 346233 # Number of row buffer hits during reads system.physmem.writeRowHits 206899 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 70.48 # Row buffer hit rate for writes system.physmem.avgGap 674657.38 # Average gap between requests system.membus.throughput 94862960 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 178738 # Transaction distribution system.membus.trans_dist::ReadResp 178738 # Transaction distribution system.membus.trans_dist::Writeback 293576 # Transaction distribution system.membus.trans_dist::UpgradeReq 131239 # Transaction distribution system.membus.trans_dist::UpgradeResp 131239 # Transaction distribution system.membus.trans_dist::ReadExReq 206848 # Transaction distribution system.membus.trans_dist::ReadExResp 206848 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 43466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 3389530500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 3902075273 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.branchPred.lookups 205568854 # Number of BP lookups system.cpu.branchPred.condPredicted 205568854 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 9898045 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 117107860 # Number of BTB lookups system.cpu.branchPred.BTBHits 114698140 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 97.942307 # BTB Hit Percentage system.cpu.branchPred.usedRAS 25050036 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1792384 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 916561947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 167337624 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1131632693 # Number of instructions fetch has processed system.cpu.fetch.Branches 205568854 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 139748176 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 352252174 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 71070724 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 303559378 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 48756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 256407 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 161987307 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 2533545 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 884373851 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.380748 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.325183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 536185326 60.63% 60.63% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 23385873 2.64% 63.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 25265986 2.86% 66.13% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 27892803 3.15% 69.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 17753666 2.01% 71.29% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 22918818 2.59% 73.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 29434810 3.33% 77.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 26635470 3.01% 80.22% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 174901099 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 884373851 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.224283 # Number of branch fetches per cycle system.cpu.fetch.rate 1.234649 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 222568980 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 258608644 # Number of cycles decode is blocked system.cpu.decode.RunCycles 295229836 # Number of cycles decode is running system.cpu.decode.UnblockCycles 47046921 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 60919470 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2071205121 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 60919470 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 255995647 # Number of cycles rename is idle system.cpu.rename.BlockCycles 114297250 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16886 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 306709824 # Number of cycles rename is running system.cpu.rename.UnblockCycles 146434774 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2035062210 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 18307 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 24837229 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 106300367 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 2137993094 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5150291705 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 5150182226 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 109479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 523952240 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1150 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 1079 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 346047502 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 495816702 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 194427613 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 195309908 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 54766711 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1975264807 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13440 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1772060023 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 484597 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 441400489 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 734643480 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12888 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 884373851 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.003745 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.883277 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 267848230 30.29% 30.29% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 151701849 17.15% 47.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 137335256 15.53% 62.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 131820581 14.91% 77.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 91575970 10.35% 88.23% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 56038061 6.34% 94.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 34420312 3.89% 98.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 11858874 1.34% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1774718 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 884373851 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4913366 32.39% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 7647346 50.41% 82.79% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2610757 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2623506 0.15% 0.15% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1165695577 65.78% 65.93% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 352860 0.02% 65.95% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 3880836 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 429278718 24.22% 90.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 170228526 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1772060023 # Type of FU issued system.cpu.iq.rate 1.933377 # Inst issue rate system.cpu.iq.fu_busy_cnt 15171469 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008561 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 4444135081 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2416902562 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1744830840 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 32680 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 3547 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1784600923 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7063 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 172561564 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 111714545 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 391852 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 328370 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 45268501 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 14755 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 580 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 60919470 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 66677729 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 7180416 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 1975278247 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 784703 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 495816702 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 194428687 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 3345 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4482902 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 83440 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 328370 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 5898868 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 4425517 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 10324385 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 1752929949 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 424141217 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 19130074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 590928526 # number of memory reference insts executed system.cpu.iew.exec_branches 167466016 # Number of branches executed system.cpu.iew.exec_stores 166787309 # Number of stores executed system.cpu.iew.exec_rate 1.912506 # Inst execution rate system.cpu.iew.wb_sent 1749673980 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1744834387 # cumulative count of insts written-back system.cpu.iew.wb_producers 1325007870 # num instructions producing a value system.cpu.iew.wb_consumers 1945707966 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.903673 # insts written-back per cycle system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 446317369 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 9927482 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 823454381 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.856798 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.436978 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 331487662 40.26% 40.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 193224596 23.47% 63.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 63171510 7.67% 71.39% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92561504 11.24% 82.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 24941236 3.03% 85.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 27475920 3.34% 89.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 9375370 1.14% 90.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 11392855 1.38% 91.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 69823728 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 823454381 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262343 # Number of memory references committed system.cpu.commit.loads 384102157 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. system.cpu.commit.bw_lim_events 69823728 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 2728936723 # The number of ROB reads system.cpu.rob.rob_writes 4011692646 # The number of ROB writes system.cpu.timesIdled 3353511 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 32188096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated system.cpu.cpi 1.108462 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.108462 # CPI: Total CPI of All Threads system.cpu.ipc 0.902151 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.902151 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3313440054 # number of integer regfile reads system.cpu.int_regfile_writes 1825840966 # number of integer regfile writes system.cpu.fp_regfile_reads 3533 # number of floating regfile reads system.cpu.fp_regfile_writes 16 # number of floating regfile writes system.cpu.misc_regfile_reads 964658774 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 698991407 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1901821 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1901820 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2330756 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 209959241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 5293 # number of replacements system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 161845824 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 161845824 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 161845824 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 161845824 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 161845824 # number of overall hits system.cpu.icache.overall_hits::total 161845824 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 141483 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 141483 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 141483 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 141483 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 141483 # number of overall misses system.cpu.icache.overall_misses::total 141483 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 929611982 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 929611982 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 929611982 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 929611982 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 929611982 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 929611982 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 161987307 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 161987307 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 161987307 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 161987307 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 161987307 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 161987307 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000873 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000873 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000873 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000873 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000873 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6570.485373 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 6570.485373 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 6570.485373 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 6570.485373 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 6570.485373 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 6570.485373 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 297 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 49.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1954 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1954 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1954 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1954 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1954 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1954 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 139529 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 139529 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 139529 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 139529 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 139529 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 139529 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 557299259 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 557299259 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 557299259 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 557299259 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 557299259 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 557299259 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000861 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000861 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000861 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3994.146443 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3994.146443 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3994.146443 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 3994.146443 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3994.146443 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 3994.146443 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 352905 # number of replacements system.cpu.l2cache.tags.tagsinuse 29673.331814 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3696859 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 385269 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.595527 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 199076310000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21119.362848 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.841801 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 8330.127165 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.644512 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006831 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.254215 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.905558 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3661 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1586701 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1590362 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2330756 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2330756 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1409 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1409 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 564916 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 564916 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 3661 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2151617 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2155278 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3661 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2151617 # number of overall hits system.cpu.l2cache.overall_hits::total 2155278 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3148 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 175591 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 178739 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 131219 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 131219 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 206868 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206868 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3148 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 382459 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 385607 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3148 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 382459 # number of overall misses system.cpu.l2cache.overall_misses::total 385607 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244818000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13237623957 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 13482441957 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6766209 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 6766209 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14252139980 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 14252139980 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 244818000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 27489763937 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 27734581937 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 244818000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 27489763937 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 27734581937 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6809 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1762292 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1769101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2330756 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2330756 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 132628 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 132628 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 771784 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 771784 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 6809 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2534076 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2540885 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 6809 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2534076 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2540885 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462329 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099638 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.101034 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989376 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989376 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268039 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.268039 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462329 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.150926 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.151761 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462329 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150926 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151761 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77769.377382 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75388.966160 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 75430.890611 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51.564248 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51.564248 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68894.850726 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68894.850726 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77769.377382 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71876.368283 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 71924.477349 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77769.377382 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71876.368283 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 71924.477349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 293576 # number of writebacks system.cpu.l2cache.writebacks::total 293576 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3148 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175591 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 178739 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 131219 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 131219 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206868 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206868 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3148 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 382459 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 385607 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 382459 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 385607 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205059000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10984214957 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11189273957 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1316213142 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1316213142 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11623719520 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11623719520 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205059000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22607934477 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 22812993477 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205059000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22607934477 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 22812993477 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099638 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989376 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989376 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268039 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268039 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.151761 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65139.453621 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62555.683133 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62601.189203 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.659752 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.659752 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56189.065104 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56189.065104 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65139.453621 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65139.453621 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 2529980 # number of replacements system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148239061 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 395579138 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 395579138 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 395579138 # number of overall hits system.cpu.dcache.overall_hits::total 395579138 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2863342 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2863342 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 921141 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 921141 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 3784483 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3784483 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3784483 # number of overall misses system.cpu.dcache.overall_misses::total 3784483 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 57420164907 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 57420164907 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 25863644657 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 25863644657 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 83283809564 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 83283809564 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 83283809564 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 83283809564 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250203419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250203419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 399363621 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 399363621 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 399363621 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 399363621 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006176 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006176 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009476 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009476 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009476 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009476 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.547535 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.547535 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28077.834617 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 28077.834617 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 22006.654427 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 22006.654427 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 7199 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.571219 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2330756 # number of writebacks system.cpu.dcache.writebacks::total 2330756 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100793 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1100793 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16986 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 16986 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1117779 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1117779 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1117779 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1117779 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762549 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1762549 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 904155 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 904155 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2666704 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2666704 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2666704 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2666704 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30902624251 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 30902624251 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23743181593 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 23743181593 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54645805844 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 54645805844 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54645805844 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 54645805844 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006062 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006062 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006677 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006677 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17532.916390 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17532.916390 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26260.078850 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26260.078850 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------