---------- Begin Simulation Statistics ---------- sim_seconds 2.853344 # Number of seconds simulated sim_ticks 2853343899500 # Number of ticks simulated final_tick 2853343899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 139312 # Simulator instruction rate (inst/s) host_op_rate 168444 # Simulator op (including micro ops) rate (op/s) host_tick_rate 3544495637 # Simulator tick rate (ticks/s) host_mem_usage 589148 # Number of bytes of host memory used host_seconds 805.01 # Real time elapsed on the host sim_insts 112146750 # Number of instructions simulated sim_ops 135598813 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1675712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9177004 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10861420 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1675712 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1675712 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7976832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::total 7994356 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 26183 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 143912 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 170231 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 124638 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 129019 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 587280 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3216228 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3806558 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 587280 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 587280 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2795608 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6142 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2801750 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2795608 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 587280 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3222369 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6608308 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 170231 # Number of read requests accepted system.physmem.writeReqs 129019 # Number of write requests accepted system.physmem.readBursts 170231 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 129019 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10886144 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue system.physmem.bytesWritten 8006976 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10861420 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7994356 # Total written bytes from the system interface side system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10508 # Per bank write bursts system.physmem.perBankRdBursts::1 10518 # Per bank write bursts system.physmem.perBankRdBursts::2 10699 # Per bank write bursts system.physmem.perBankRdBursts::3 10590 # Per bank write bursts system.physmem.perBankRdBursts::4 13367 # Per bank write bursts system.physmem.perBankRdBursts::5 10649 # Per bank write bursts system.physmem.perBankRdBursts::6 10947 # Per bank write bursts system.physmem.perBankRdBursts::7 11320 # Per bank write bursts system.physmem.perBankRdBursts::8 10289 # Per bank write bursts system.physmem.perBankRdBursts::9 10353 # Per bank write bursts system.physmem.perBankRdBursts::10 10214 # Per bank write bursts system.physmem.perBankRdBursts::11 9210 # Per bank write bursts system.physmem.perBankRdBursts::12 10497 # Per bank write bursts system.physmem.perBankRdBursts::13 11112 # Per bank write bursts system.physmem.perBankRdBursts::14 10041 # Per bank write bursts system.physmem.perBankRdBursts::15 9782 # Per bank write bursts system.physmem.perBankWrBursts::0 7781 # Per bank write bursts system.physmem.perBankWrBursts::1 7920 # Per bank write bursts system.physmem.perBankWrBursts::2 8383 # Per bank write bursts system.physmem.perBankWrBursts::3 8149 # Per bank write bursts system.physmem.perBankWrBursts::4 7457 # Per bank write bursts system.physmem.perBankWrBursts::5 7755 # Per bank write bursts system.physmem.perBankWrBursts::6 7974 # Per bank write bursts system.physmem.perBankWrBursts::7 8419 # Per bank write bursts system.physmem.perBankWrBursts::8 7882 # Per bank write bursts system.physmem.perBankWrBursts::9 7909 # Per bank write bursts system.physmem.perBankWrBursts::10 7627 # Per bank write bursts system.physmem.perBankWrBursts::11 7117 # Per bank write bursts system.physmem.perBankWrBursts::12 7926 # Per bank write bursts system.physmem.perBankWrBursts::13 8274 # Per bank write bursts system.physmem.perBankWrBursts::14 7391 # Per bank write bursts system.physmem.perBankWrBursts::15 7145 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 4 # Number of times write queue was full causing retry system.physmem.totGap 2853343449000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 169674 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 124638 # Write request sizes (log2) system.physmem.rdQLenPdf::0 162184 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 7619 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 281 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1927 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2883 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6085 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 6461 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6753 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6861 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 7240 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7833 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 7817 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 8977 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9286 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 7605 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 7322 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 7382 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6746 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 6645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 179 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 175 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 60538 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 312.085896 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 184.679507 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 329.366687 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 22012 36.36% 36.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 14640 24.18% 60.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 6552 10.82% 71.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3435 5.67% 77.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2639 4.36% 81.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1745 2.88% 84.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1057 1.75% 86.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7396 12.22% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 60538 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 27.253805 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 580.495916 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 6239 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 20.046307 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 18.379346 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 13.281323 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 5473 87.69% 87.69% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 55 0.88% 88.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 66 1.06% 89.63% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 37 0.59% 90.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 284 4.55% 94.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 48 0.77% 95.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 17 0.27% 95.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 11 0.18% 95.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 9 0.14% 96.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 6 0.10% 96.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 4 0.06% 96.30% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 13 0.21% 96.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 157 2.52% 99.02% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 4 0.06% 99.09% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 3 0.05% 99.13% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 5 0.08% 99.21% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 5 0.08% 99.29% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 2 0.03% 99.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 1 0.02% 99.34% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 4 0.06% 99.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.02% 99.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.02% 99.44% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 8 0.13% 99.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 15 0.24% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 2 0.03% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.02% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 3 0.05% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads system.physmem.totQLat 1691091750 # Total ticks spent queuing system.physmem.totMemAccLat 4880391750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 850480000 # Total ticks spent in databus transfers system.physmem.avgQLat 9941.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 28691.98 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.93 # Average write queue length when enqueuing system.physmem.readRowHits 140142 # Number of row buffer hits during reads system.physmem.writeRowHits 94524 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.39 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes system.physmem.avgGap 9534982.29 # Average gap between requests system.physmem.pageHitRate 79.49 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 235894680 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 128712375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 691064400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 413670240 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 83561921055 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1638705050250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 1910102702040 # Total energy per rank (pJ) system.physmem_0.averagePower 669.426569 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 2725994839000 # Time in different power states system.physmem_0.memoryStateTime::REF 95279340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 32067469750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 635676600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 397036080 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 82367679285 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 1639752630750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 1909862191230 # Total energy per rank (pJ) system.physmem_1.averagePower 669.342278 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 2727746913750 # Time in different power states system.physmem_1.memoryStateTime::REF 95279340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 30317548250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.bridge.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu.branchPred.lookups 31062999 # Number of BP lookups system.cpu.branchPred.condPredicted 16869066 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2486744 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 18728785 # Number of BTB lookups system.cpu.branchPred.BTBHits 10415318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 55.611285 # BTB Hit Percentage system.cpu.branchPred.usedRAS 7833584 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1520957 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 3075291 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2886933 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 188358 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 109527 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 68003 # Table walker walks requested system.cpu.dtb.walker.walksShort 68003 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44606 # Level at which table walker walks with short descriptors terminate system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23397 # Level at which table walker walks with short descriptors terminate system.cpu.dtb.walker.walkWaitTime::samples 68003 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::0 68003 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 68003 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::mean 10035.266557 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::gmean 8419.099443 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::stdev 6813.200210 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-16383 7021 88.91% 88.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::16384-32767 869 11.00% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 271390000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 271390000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 271390000 # Table walker pending requests distribution system.cpu.dtb.walker.walkPageSizes::4K 6503 82.35% 82.35% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::1M 1394 17.65% 100.00% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68003 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68003 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 75900 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 24771188 # DTB read hits system.cpu.dtb.read_misses 61134 # DTB read misses system.cpu.dtb.write_hits 19449290 # DTB write hits system.cpu.dtb.write_misses 6869 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 1418 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 770 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 24832322 # DTB read accesses system.cpu.dtb.write_accesses 19456159 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 44220478 # DTB hits system.cpu.dtb.misses 68003 # DTB misses system.cpu.dtb.accesses 44288481 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 5856 # Table walker walks requested system.cpu.itb.walker.walksShort 5856 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 5531 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walkWaitTime::samples 5856 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::0 5856 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 5856 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3193 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::mean 10411.838396 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::gmean 8598.635311 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::stdev 6896.589649 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::0-8191 1843 57.72% 57.72% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::8192-16383 807 25.27% 82.99% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::16384-24575 535 16.76% 99.75% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::24576-32767 7 0.22% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3193 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 270980500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 270980500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 270980500 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 2883 90.29% 90.29% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3193 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5856 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 5856 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3193 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3193 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 57483193 # ITB inst hits system.cpu.itb.inst_misses 5856 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 2912 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 8279 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 57489049 # ITB inst accesses system.cpu.itb.hits 57483193 # DTB hits system.cpu.itb.misses 5856 # DTB misses system.cpu.itb.accesses 57489049 # DTB accesses system.cpu.numPwrStateTransitions 6066 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::mean 888351102.639301 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::stdev 17445509399.919735 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499967553028 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state system.cpu.pwrStateResidencyTicks::ON 158975005195 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::CLK_GATED 2694368894305 # Cumulative time (in ticks) in various power states system.cpu.numCycles 317952965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 112146750 # Number of instructions committed system.cpu.committedOps 135598813 # Number of ops (including micro ops) committed system.cpu.discardedOps 7821624 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching system.cpu.quiesceCycles 5388799101 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.cpi 2.835151 # CPI: cycles per instruction system.cpu.ipc 0.352715 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 90918529 67.05% 67.05% # Class of committed instruction system.cpu.op_class_0::IntMult 113133 0.08% 67.13% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatMisc 8487 0.01% 67.14% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction system.cpu.op_class_0::MemRead 24279497 17.91% 85.05% # Class of committed instruction system.cpu.op_class_0::MemWrite 20276830 14.95% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 135598813 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed system.cpu.tickCycles 217828985 # Number of cycles that the object actually ticked system.cpu.idleCycles 100123980 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 845168 # number of replacements system.cpu.dcache.tags.tagsinuse 511.946266 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42678256 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 845680 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 50.466200 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 322165500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.946266 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999895 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999895 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 176368054 # Number of tag accesses system.cpu.dcache.tags.data_accesses 176368054 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 23126363 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23126363 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18288488 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18288488 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 357151 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 357151 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 443374 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 443374 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 459996 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 459996 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 41414851 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 41414851 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 41772002 # number of overall hits system.cpu.dcache.overall_hits::total 41772002 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 466466 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 466466 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 547177 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 547177 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 169147 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 169147 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 22423 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22423 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses system.cpu.dcache.demand_misses::cpu.data 1013643 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1013643 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1182790 # number of overall misses system.cpu.dcache.overall_misses::total 1182790 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 6859105500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 6859105500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 23368526480 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 23368526480 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290513500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 290513500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 30227631980 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 30227631980 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 30227631980 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30227631980 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 23592829 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 23592829 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18835665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 18835665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 526298 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 526298 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465797 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465797 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 459998 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 459998 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 42428494 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42428494 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42954792 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42954792 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019772 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.019772 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029050 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.029050 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321390 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.321390 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048139 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048139 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023891 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.023891 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14704.406109 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14704.406109 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42707.435583 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 42707.435583 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12956.049592 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12956.049592 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 29820.786983 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29820.786983 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 25556.211990 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 25556.211990 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 700399 # number of writebacks system.cpu.dcache.writebacks::total 700399 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45619 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 45619 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 248851 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 248851 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14095 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14095 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 294470 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 294470 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 294470 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 294470 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 420847 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 420847 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298326 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 298326 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121014 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 121014 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8328 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8328 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 719173 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 719173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 840187 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 840187 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6004353500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6004353500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12472700000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 12472700000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1605906500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1605906500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 111255000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111255000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18477053500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 18477053500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20082960000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 20082960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6301797000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6301797000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6301797000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 6301797000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017838 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017838 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015838 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015838 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229934 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229934 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017879 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017879 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016950 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.016950 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019560 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.019560 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14267.307359 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14267.307359 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41808.960667 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41808.960667 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.419125 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.419125 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13359.149856 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13359.149856 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25692.084519 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 25692.084519 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23902.964459 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 23902.964459 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202447.860447 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.860447 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107335.882543 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107335.882543 # average overall mshr uncacheable latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2889133 # number of replacements system.cpu.icache.tags.tagsinuse 511.392140 # Cycle average of tags in use system.cpu.icache.tags.total_refs 54584955 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2889645 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.889848 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 15688442500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.392140 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998813 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998813 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 60364268 # Number of tag accesses system.cpu.icache.tags.data_accesses 60364268 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 54584955 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 54584955 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 54584955 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 54584955 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 54584955 # number of overall hits system.cpu.icache.overall_hits::total 54584955 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2889657 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2889657 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2889657 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 2889657 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2889657 # number of overall misses system.cpu.icache.overall_misses::total 2889657 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 39245614500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 39245614500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 39245614500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 39245614500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 39245614500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 39245614500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 57474612 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 57474612 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 57474612 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 57474612 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 57474612 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 57474612 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050277 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.050277 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.050277 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.050277 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.050277 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.050277 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13581.409316 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 13581.409316 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13581.409316 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 13581.409316 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13581.409316 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13581.409316 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2889133 # number of writebacks system.cpu.icache.writebacks::total 2889133 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889657 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 2889657 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 2889657 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 2889657 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2889657 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2889657 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3267 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3267 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3267 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3267 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36355958500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 36355958500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36355958500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 36355958500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36355958500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 36355958500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 258265000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 258265000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 258265000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 258265000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050277 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.050277 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.050277 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12581.409662 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12581.409662 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12581.409662 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 12581.409662 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12581.409662 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12581.409662 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 79052.647689 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 79052.647689 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 79052.647689 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 79052.647689 # average overall mshr uncacheable latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96859 # number of replacements system.cpu.l2cache.tags.tagsinuse 65151.144064 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7317028 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 162271 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 45.091409 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 94922732000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.044406 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 12290.016649 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 52791.059572 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001069 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.187531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.805528 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994128 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65349 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 63 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 80 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60668 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000961 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997147 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 60051875 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 60051875 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67793 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3314 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 71107 # number of ReadReq hits system.cpu.l2cache.WritebackDirty_hits::writebacks 700399 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 700399 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2838445 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 2838445 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 2804 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 2804 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 166282 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 166282 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866680 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2866680 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 535530 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 535530 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 67793 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3314 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 2866680 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 701812 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3639599 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 67793 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3314 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 2866680 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 701812 # number of overall hits system.cpu.l2cache.overall_hits::total 3639599 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 120 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 121 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 129240 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 129240 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22945 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 22945 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14654 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 14654 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 120 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 22945 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 143894 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 166960 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 120 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 22945 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 143894 # number of overall misses system.cpu.l2cache.overall_misses::total 166960 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10289000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 10372500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 145500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 145500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10239764000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 10239764000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1854577500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 1854577500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1232673000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1232673000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10289000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1854577500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 11472437000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 13337387000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10289000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1854577500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 11472437000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 13337387000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67913 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 700399 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 700399 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2838445 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 2838445 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2809 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2809 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 295522 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 295522 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889625 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 2889625 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 550184 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 550184 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67913 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3315 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 2889625 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 845706 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 3806559 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67913 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3315 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 2889625 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 845706 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 3806559 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001767 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000302 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001699 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001780 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001780 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437328 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.437328 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007940 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007940 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026635 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026635 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001767 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000302 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007940 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.170147 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.043861 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001767 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000302 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007940 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.170147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.043861 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.666667 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 85723.140496 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29100 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29100 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79230.609718 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79230.609718 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80827.086511 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80827.086511 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84118.534189 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84118.534189 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.666667 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80827.086511 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79728.390343 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 79883.726641 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.666667 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80827.086511 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79728.390343 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 79883.726641 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 88448 # number of writebacks system.cpu.l2cache.writebacks::total 88448 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 18 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 136 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 136 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 136 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 136 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 154 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 120 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 121 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129240 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 129240 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22927 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22927 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14518 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14518 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 120 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 22927 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 143758 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 166806 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 120 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 22927 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 143758 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 166806 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3267 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34395 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3267 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61978 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9089000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 73500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9162500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 95500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 95500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8947364000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8947364000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1624414500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1624414500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1078119000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1078119000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9089000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 73500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1624414500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10025483000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 11659060000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9089000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 73500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1624414500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10025483000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 11659060000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 207499500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5912622000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6120121500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 207499500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5912622000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6120121500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001780 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437328 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437328 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026388 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026388 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.043821 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.043821 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75723.140496 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19100 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19100 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69230.609718 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69230.609718 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70851.594190 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70851.594190 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74260.848602 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74260.848602 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189945.451041 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 177936.371566 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100707.226925 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98746.676240 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 7504035 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768706 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58030 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 170 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 170 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 137182 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3577165 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 788847 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2889133 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 153180 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2809 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 295522 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 295522 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889657 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 550405 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8674948 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2659767 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14702 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159313 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 11508730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370049536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99142941 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13260 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271652 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 469477389 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 133226 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5798108 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 4004431 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.022424 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.148057 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 3914637 97.76% 97.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 89794 2.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4004431 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 7421943500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 275377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4339894977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1315039189 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 11390493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 91431936 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 46364500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 618000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 6096500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 39117500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 187733842 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements system.iocache.tags.tagsinuse 1.032370 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 270830421000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ide 1.032370 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.064523 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.064523 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses system.iocache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 29494377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 29494377 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4278402465 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4278402465 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 4307896842 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 4307896842 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 4307896842 # number of overall miss cycles system.iocache.overall_miss_latency::total 4307896842 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 126044.346154 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126044.346154 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118109.608685 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 118109.608685 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency system.iocache.demand_avg_miss_latency::total 118160.536563 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency system.iocache.overall_avg_miss_latency::total 118160.536563 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 17794377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 17794377 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465093924 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2465093924 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 2482888301 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 2482888301 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 2482888301 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 2482888301 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76044.346154 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76044.346154 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68051.400287 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68051.400287 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 336558 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 137845 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34395 # Transaction distribution system.membus.trans_dist::ReadResp 72195 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution system.membus.trans_dist::WritebackDirty 124638 # Transaction distribution system.membus.trans_dist::CleanEvict 8645 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 129117 # Transaction distribution system.membus.trans_dist::ReadExResp 129117 # Transaction distribution system.membus.trans_dist::ReadSharedReq 37800 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446466 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554028 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 626925 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16538656 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16702429 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 19019549 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 504 # Total snoops (count) system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 265249 # Request fanout histogram system.membus.snoop_fanout::mean 0.018541 # Request fanout histogram system.membus.snoop_fanout::stdev 0.134898 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 260331 98.15% 98.15% # Request fanout histogram system.membus.snoop_fanout::1 4918 1.85% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 265249 # Request fanout histogram system.membus.reqLayer0.occupancy 92904500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 906764526 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 989491000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1228623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ----------