[root] type=Root children=system eventq_index=0 full_system=true sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 boot_loader=/arm/projectscratch/pd/sysrandd/dist/binaries/boot.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 kernel=/arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 readfile=tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 master=system.iobus.slave[0] slave=system.membus.master[0] [system.cf0] type=IdeDisk children=image delay=1000000 driveID=master eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 image_file=/arm/projectscratch/pd/sysrandd/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] type=MinorCPU children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer branchPred=system.cpu0.branchPred checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb enableIdling=true eventq_index=0 executeAllowEarlyMemoryIssue=true executeBranchDelay=1 executeCommitLimit=2 executeCycleInput=true executeFuncUnits=system.cpu0.executeFuncUnits executeInputBufferSize=7 executeInputWidth=2 executeIssueLimit=2 executeLSQMaxStoreBufferStoresPerCycle=2 executeLSQRequestsQueueSize=1 executeLSQStoreBufferSize=5 executeLSQTransfersQueueSize=2 executeMaxAccessesInMemory=2 executeMemoryCommitLimit=1 executeMemoryIssueLimit=1 executeMemoryWidth=0 executeSetTraceTimeOnCommit=true executeSetTraceTimeOnIssue=false fetch1FetchLimit=1 fetch1LineSnapWidth=0 fetch1LineWidth=0 fetch1ToFetch2BackwardDelay=1 fetch1ToFetch2ForwardDelay=1 fetch2CycleInput=true fetch2InputBufferSize=2 fetch2ToDecodeForwardDelay=1 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.branchPred] type=BranchPredictor BTBEntries=4096 BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 predType=tournament [system.cpu0.dcache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] [system.cpu0.dcache.tags] type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 sequential_access=false size=32768 [system.cpu0.dstage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb tlb=system.cpu0.dtb [system.cpu0.dstage2_mmu.stage2_tlb] type=ArmTLB children=walker eventq_index=0 is_stage2=true size=32 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 is_stage2=false size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] [system.cpu0.executeFuncUnits] type=MinorFUPool children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 eventq_index=0 funcUnits=system.cpu0.executeFuncUnits.funcUnits0 system.cpu0.executeFuncUnits.funcUnits1 system.cpu0.executeFuncUnits.funcUnits2 system.cpu0.executeFuncUnits.funcUnits3 system.cpu0.executeFuncUnits.funcUnits4 system.cpu0.executeFuncUnits.funcUnits5 system.cpu0.executeFuncUnits.funcUnits6 [system.cpu0.executeFuncUnits.funcUnits0] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses opLat=3 timings=system.cpu0.executeFuncUnits.funcUnits0.timings [system.cpu0.executeFuncUnits.funcUnits0.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses [system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntAlu [system.cpu0.executeFuncUnits.funcUnits0.timings] type=MinorFUTiming children=opClasses description=Int eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses srcRegsRelativeLats=2 suppress=false [system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu0.executeFuncUnits.funcUnits1] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses opLat=3 timings=system.cpu0.executeFuncUnits.funcUnits1.timings [system.cpu0.executeFuncUnits.funcUnits1.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses [system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntAlu [system.cpu0.executeFuncUnits.funcUnits1.timings] type=MinorFUTiming children=opClasses description=Int eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses srcRegsRelativeLats=2 suppress=false [system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu0.executeFuncUnits.funcUnits2] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses opLat=3 timings=system.cpu0.executeFuncUnits.funcUnits2.timings [system.cpu0.executeFuncUnits.funcUnits2.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses [system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntMult [system.cpu0.executeFuncUnits.funcUnits2.timings] type=MinorFUTiming children=opClasses description=Mul eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses srcRegsRelativeLats=0 suppress=false [system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu0.executeFuncUnits.funcUnits3] type=MinorFU children=opClasses eventq_index=0 issueLat=9 opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses opLat=9 timings= [system.cpu0.executeFuncUnits.funcUnits3.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses [system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntDiv [system.cpu0.executeFuncUnits.funcUnits4] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses opLat=6 timings=system.cpu0.executeFuncUnits.funcUnits4.timings [system.cpu0.executeFuncUnits.funcUnits4.opClasses] type=MinorOpClassSet children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00] type=MinorOpClass eventq_index=0 opClass=FloatAdd [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01] type=MinorOpClass eventq_index=0 opClass=FloatCmp [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02] type=MinorOpClass eventq_index=0 opClass=FloatCvt [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03] type=MinorOpClass eventq_index=0 opClass=FloatMult [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04] type=MinorOpClass eventq_index=0 opClass=FloatDiv [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05] type=MinorOpClass eventq_index=0 opClass=FloatSqrt [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06] type=MinorOpClass eventq_index=0 opClass=SimdAdd [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07] type=MinorOpClass eventq_index=0 opClass=SimdAddAcc [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08] type=MinorOpClass eventq_index=0 opClass=SimdAlu [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09] type=MinorOpClass eventq_index=0 opClass=SimdCmp [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10] type=MinorOpClass eventq_index=0 opClass=SimdCvt [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11] type=MinorOpClass eventq_index=0 opClass=SimdMisc [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12] type=MinorOpClass eventq_index=0 opClass=SimdMult [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13] type=MinorOpClass eventq_index=0 opClass=SimdMultAcc [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14] type=MinorOpClass eventq_index=0 opClass=SimdShift [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15] type=MinorOpClass eventq_index=0 opClass=SimdShiftAcc [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16] type=MinorOpClass eventq_index=0 opClass=SimdSqrt [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17] type=MinorOpClass eventq_index=0 opClass=SimdFloatAdd [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18] type=MinorOpClass eventq_index=0 opClass=SimdFloatAlu [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19] type=MinorOpClass eventq_index=0 opClass=SimdFloatCmp [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20] type=MinorOpClass eventq_index=0 opClass=SimdFloatCvt [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21] type=MinorOpClass eventq_index=0 opClass=SimdFloatDiv [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22] type=MinorOpClass eventq_index=0 opClass=SimdFloatMisc [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23] type=MinorOpClass eventq_index=0 opClass=SimdFloatMult [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24] type=MinorOpClass eventq_index=0 opClass=SimdFloatMultAcc [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25] type=MinorOpClass eventq_index=0 opClass=SimdFloatSqrt [system.cpu0.executeFuncUnits.funcUnits4.timings] type=MinorFUTiming children=opClasses description=FloatSimd eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses srcRegsRelativeLats=2 suppress=false [system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu0.executeFuncUnits.funcUnits5] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses opLat=1 timings=system.cpu0.executeFuncUnits.funcUnits5.timings [system.cpu0.executeFuncUnits.funcUnits5.opClasses] type=MinorOpClassSet children=opClasses0 opClasses1 eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0] type=MinorOpClass eventq_index=0 opClass=MemRead [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1] type=MinorOpClass eventq_index=0 opClass=MemWrite [system.cpu0.executeFuncUnits.funcUnits5.timings] type=MinorFUTiming children=opClasses description=Mem eventq_index=0 extraAssumedLat=2 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses srcRegsRelativeLats=1 suppress=false [system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu0.executeFuncUnits.funcUnits6] type=MinorFU children=opClasses eventq_index=0 issueLat=1 opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses opLat=1 timings= [system.cpu0.executeFuncUnits.funcUnits6.opClasses] type=MinorOpClassSet children=opClasses0 opClasses1 eventq_index=0 opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1 [system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0] type=MinorOpClass eventq_index=0 opClass=IprAccess [system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1] type=MinorOpClass eventq_index=0 opClass=InstPrefetch [system.cpu0.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] [system.cpu0.icache.tags] type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 sequential_access=false size=32768 [system.cpu0.interrupts] type=ArmInterrupts eventq_index=0 [system.cpu0.isa] type=ArmISA eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 id_aa64afr1_el1=0 id_aa64dfr0_el1=1052678 id_aa64dfr1_el1=0 id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 id_aa64pfr0_el1=17 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 system=system [system.cpu0.istage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb tlb=system.cpu0.itb [system.cpu0.istage2_mmu.stage2_tlb] type=ArmTLB children=walker eventq_index=0 is_stage2=true size=32 walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 is_stage2=false size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer eventq_index=0 [system.cpu1] type=MinorCPU children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer branchPred=system.cpu1.branchPred checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb enableIdling=true eventq_index=0 executeAllowEarlyMemoryIssue=true executeBranchDelay=1 executeCommitLimit=2 executeCycleInput=true executeFuncUnits=system.cpu1.executeFuncUnits executeInputBufferSize=7 executeInputWidth=2 executeIssueLimit=2 executeLSQMaxStoreBufferStoresPerCycle=2 executeLSQRequestsQueueSize=1 executeLSQStoreBufferSize=5 executeLSQTransfersQueueSize=2 executeMaxAccessesInMemory=2 executeMemoryCommitLimit=1 executeMemoryIssueLimit=1 executeMemoryWidth=0 executeSetTraceTimeOnCommit=true executeSetTraceTimeOnIssue=false fetch1FetchLimit=1 fetch1LineSnapWidth=0 fetch1LineWidth=0 fetch1ToFetch2BackwardDelay=1 fetch1ToFetch2ForwardDelay=1 fetch2CycleInput=true fetch2InputBufferSize=2 fetch2ToDecodeForwardDelay=1 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= switched_out=false system=system tracer=system.cpu1.tracer workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.branchPred] type=BranchPredictor BTBEntries=4096 BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 predType=tournament [system.cpu1.dcache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 sequential_access=false size=32768 [system.cpu1.dstage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb tlb=system.cpu1.dtb [system.cpu1.dstage2_mmu.stage2_tlb] type=ArmTLB children=walker eventq_index=0 is_stage2=true size=32 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[11] [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 is_stage2=false size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[9] [system.cpu1.executeFuncUnits] type=MinorFUPool children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 eventq_index=0 funcUnits=system.cpu1.executeFuncUnits.funcUnits0 system.cpu1.executeFuncUnits.funcUnits1 system.cpu1.executeFuncUnits.funcUnits2 system.cpu1.executeFuncUnits.funcUnits3 system.cpu1.executeFuncUnits.funcUnits4 system.cpu1.executeFuncUnits.funcUnits5 system.cpu1.executeFuncUnits.funcUnits6 [system.cpu1.executeFuncUnits.funcUnits0] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses opLat=3 timings=system.cpu1.executeFuncUnits.funcUnits0.timings [system.cpu1.executeFuncUnits.funcUnits0.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses [system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntAlu [system.cpu1.executeFuncUnits.funcUnits0.timings] type=MinorFUTiming children=opClasses description=Int eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses srcRegsRelativeLats=2 suppress=false [system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu1.executeFuncUnits.funcUnits1] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses opLat=3 timings=system.cpu1.executeFuncUnits.funcUnits1.timings [system.cpu1.executeFuncUnits.funcUnits1.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses [system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntAlu [system.cpu1.executeFuncUnits.funcUnits1.timings] type=MinorFUTiming children=opClasses description=Int eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses srcRegsRelativeLats=2 suppress=false [system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu1.executeFuncUnits.funcUnits2] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses opLat=3 timings=system.cpu1.executeFuncUnits.funcUnits2.timings [system.cpu1.executeFuncUnits.funcUnits2.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses [system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntMult [system.cpu1.executeFuncUnits.funcUnits2.timings] type=MinorFUTiming children=opClasses description=Mul eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses srcRegsRelativeLats=0 suppress=false [system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu1.executeFuncUnits.funcUnits3] type=MinorFU children=opClasses eventq_index=0 issueLat=9 opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses opLat=9 timings= [system.cpu1.executeFuncUnits.funcUnits3.opClasses] type=MinorOpClassSet children=opClasses eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses [system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses] type=MinorOpClass eventq_index=0 opClass=IntDiv [system.cpu1.executeFuncUnits.funcUnits4] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses opLat=6 timings=system.cpu1.executeFuncUnits.funcUnits4.timings [system.cpu1.executeFuncUnits.funcUnits4.opClasses] type=MinorOpClassSet children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00] type=MinorOpClass eventq_index=0 opClass=FloatAdd [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01] type=MinorOpClass eventq_index=0 opClass=FloatCmp [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02] type=MinorOpClass eventq_index=0 opClass=FloatCvt [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03] type=MinorOpClass eventq_index=0 opClass=FloatMult [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04] type=MinorOpClass eventq_index=0 opClass=FloatDiv [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05] type=MinorOpClass eventq_index=0 opClass=FloatSqrt [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06] type=MinorOpClass eventq_index=0 opClass=SimdAdd [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07] type=MinorOpClass eventq_index=0 opClass=SimdAddAcc [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08] type=MinorOpClass eventq_index=0 opClass=SimdAlu [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09] type=MinorOpClass eventq_index=0 opClass=SimdCmp [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10] type=MinorOpClass eventq_index=0 opClass=SimdCvt [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11] type=MinorOpClass eventq_index=0 opClass=SimdMisc [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12] type=MinorOpClass eventq_index=0 opClass=SimdMult [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13] type=MinorOpClass eventq_index=0 opClass=SimdMultAcc [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14] type=MinorOpClass eventq_index=0 opClass=SimdShift [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15] type=MinorOpClass eventq_index=0 opClass=SimdShiftAcc [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16] type=MinorOpClass eventq_index=0 opClass=SimdSqrt [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17] type=MinorOpClass eventq_index=0 opClass=SimdFloatAdd [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18] type=MinorOpClass eventq_index=0 opClass=SimdFloatAlu [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19] type=MinorOpClass eventq_index=0 opClass=SimdFloatCmp [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20] type=MinorOpClass eventq_index=0 opClass=SimdFloatCvt [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21] type=MinorOpClass eventq_index=0 opClass=SimdFloatDiv [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22] type=MinorOpClass eventq_index=0 opClass=SimdFloatMisc [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23] type=MinorOpClass eventq_index=0 opClass=SimdFloatMult [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24] type=MinorOpClass eventq_index=0 opClass=SimdFloatMultAcc [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25] type=MinorOpClass eventq_index=0 opClass=SimdFloatSqrt [system.cpu1.executeFuncUnits.funcUnits4.timings] type=MinorFUTiming children=opClasses description=FloatSimd eventq_index=0 extraAssumedLat=0 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses srcRegsRelativeLats=2 suppress=false [system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu1.executeFuncUnits.funcUnits5] type=MinorFU children=opClasses timings eventq_index=0 issueLat=1 opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses opLat=1 timings=system.cpu1.executeFuncUnits.funcUnits5.timings [system.cpu1.executeFuncUnits.funcUnits5.opClasses] type=MinorOpClassSet children=opClasses0 opClasses1 eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0] type=MinorOpClass eventq_index=0 opClass=MemRead [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1] type=MinorOpClass eventq_index=0 opClass=MemWrite [system.cpu1.executeFuncUnits.funcUnits5.timings] type=MinorFUTiming children=opClasses description=Mem eventq_index=0 extraAssumedLat=2 extraCommitLat=0 extraCommitLatExpr=Null mask=0 match=0 opClasses=system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses srcRegsRelativeLats=1 suppress=false [system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses] type=MinorOpClassSet eventq_index=0 opClasses= [system.cpu1.executeFuncUnits.funcUnits6] type=MinorFU children=opClasses eventq_index=0 issueLat=1 opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses opLat=1 timings= [system.cpu1.executeFuncUnits.funcUnits6.opClasses] type=MinorOpClassSet children=opClasses0 opClasses1 eventq_index=0 opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1 [system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0] type=MinorOpClass eventq_index=0 opClass=IprAccess [system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1] type=MinorOpClass eventq_index=0 opClass=InstPrefetch [system.cpu1.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 sequential_access=false size=32768 [system.cpu1.interrupts] type=ArmInterrupts eventq_index=0 [system.cpu1.isa] type=ArmISA eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 id_aa64afr1_el1=0 id_aa64dfr0_el1=1052678 id_aa64dfr1_el1=0 id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 id_aa64pfr0_el1=17 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 system=system [system.cpu1.istage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb tlb=system.cpu1.itb [system.cpu1.istage2_mmu.stage2_tlb] type=ArmTLB children=walker eventq_index=0 is_stage2=true size=32 walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 is_stage2=false size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 sequential_access=false size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[2] [system.iocache.tags] type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 sequential_access=false size=1024 [system.l2c] type=BaseCache children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 sequential_access=false size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.l2c.tags] type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 sequential_access=false size=4194304 [system.membus] type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access=warn pio=system.membus.default [system.physmem] type=DRAMCtrl activation_limit=4 addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 pci_cfg_base=0 system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system pio=system.membus.master[4] [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 system=system pio=system.iobus.master[21] [system.realview.cf_ctrl] type=IdeController BAR0=402653184 BAR0LegacyIO=true BAR0Size=16 BAR1=402653440 BAR1LegacyIO=true BAR1Size=1 BAR2=1 BAR2LegacyIO=false BAR2Size=8 BAR3=1 BAR3LegacyIO=false BAR3Size=4 BAR4=1 BAR4LegacyIO=false BAR4Size=16 BAR5=1 BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 DeviceID=28945 ExpansionROM=0 HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 MSICAPMsgAddr=0 MSICAPMsgCtrl=0 MSICAPMsgData=0 MSICAPMsgUpperAddr=0 MSICAPNextCapability=0 MSICAPPendingBits=0 MSIXCAPBaseOffset=0 MSIXCAPCapId=0 MSIXCAPNextCapability=0 MSIXMsgCtrl=0 MSIXPbaOffset=0 MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 PMCAPBaseOffset=0 PMCAPCapId=0 PMCAPCapabilities=0 PMCAPCtrlStatus=0 PMCAPNextCapability=0 PXCAPBaseOffset=0 PXCAPCapId=0 PXCAPCapabilities=0 PXCAPDevCap2=0 PXCAPDevCapabilities=0 PXCAPDevCtrl=0 PXCAPDevCtrl2=0 PXCAPDevStatus=0 PXCAPLinkCap=0 PXCAPLinkCtrl=0 PXCAPLinkStatus=0 PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 pci_func=0 pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] dma=system.iobus.slave[2] pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false range=2147483648:2214592511 port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 pio_latency=100000 platform=system.realview system=system terminal=system.terminal pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 system=system pio=system.iobus.master[15] [system.terminal] type=Terminal eventq_index=0 intr_control=system.intrctrl number=0 output=true port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 system=system use_default_range=false width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain eventq_index=0 voltage=1.000000