# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Ron Dreslinski

import m5
from m5.objects import *


nb_cores = 4
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]

# system simulated
system = System(cpu = cpus, physmem = RubyMemory(num_cpus=nb_cores),
                membus = Bus())

# add L1 caches
for cpu in cpus:
    cpu.connectMemPorts(system.membus)
    cpu.clock = '2GHz'

# connect memory to membus
system.physmem.port = system.membus.port


# -----------------------
# run simulation
# -----------------------

root = Root(system = system)
root.system.mem_mode = 'atomic'