# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Steve Reinhardt

import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from Caches import *

cpu = DerivO3CPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
                              L1Cache(size = '256kB'),
                              L2Cache(size = '2MB'))
# @todo Note that the L2 latency here is unmodified and 2 cycles,
# should set hit latency and response latency to 20 cycles as for
# other scripts
cpu.clock = '2GHz'

system = System(cpu = cpu,
                physmem = DDR3_1600_x64(),
                membus = CoherentBus(),
                mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)

root = Root(full_system = False, system = system)