/*
 * Copyright (c) 2016 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved
 *.
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Steve Reinhardt
 *          Nathanael Premillieu
 */

#ifndef __CPU__REG_CLASS_HH__
#define __CPU__REG_CLASS_HH__

#include <cassert>
#include <cstddef>

#include "arch/generic/types.hh"
#include "arch/registers.hh"
#include "config/the_isa.hh"

/// Enumerate the classes of registers.
enum RegClass {
    IntRegClass,        ///< Integer register
    FloatRegClass,      ///< Floating-point register
    CCRegClass,         ///< Condition-code register
    MiscRegClass        ///< Control (misc) register
};

/// Number of register classes.  This value is not part of the enum,
/// because putting it there makes the compiler complain about
/// unhandled cases in some switch statements.
const int NumRegClasses = MiscRegClass + 1;

/// Register ID: describe an architectural register with its class and index.
/// This structure is used instead of just the register index to disambiguate
/// between different classes of registers.
/// For example, a integer register with index 3 is represented by
/// Regid(IntRegClass, 3).
struct RegId {
    RegClass regClass;
    RegIndex regIdx;
    RegId() {};
    RegId(RegClass reg_class, RegIndex reg_idx)
        : regClass(reg_class), regIdx(reg_idx)
    {}

    bool operator==(const RegId& that) const {
        return regClass == that.regClass && regIdx == that.regIdx;
    }

    bool operator!=(const RegId& that) const {
        return !(*this==that);
    }

    /**
     * Returns true if this register is a zero register (needs to have a
     * constant zero value throughout the execution)
     */
    bool isZeroReg() const
    {
        return (regIdx == TheISA::ZeroReg &&
                (regClass == IntRegClass ||
                 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass)));
    }

    /**
     * Return true if this register can be renamed
     */
    bool isRenameable()
    {
        return regClass != MiscRegClass;
    }

    static const RegId zeroReg;
};

/// Map enum values to strings for debugging
extern const char *RegClassStrings[];
#endif // __CPU__REG_CLASS_HH__