def operand_types {{ 'sb' : ('signed int', 8), 'ub' : ('unsigned int', 8), 'sh' : ('signed int', 16), 'uh' : ('unsigned int', 16), 'sw' : ('signed int', 32), 'uw' : ('unsigned int', 32), 'sd' : ('signed int', 64), 'ud' : ('unsigned int', 64), 'sf' : ('float', 32), 'df' : ('float', 64), 'qf' : ('float', 128) }}; def operands {{ #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), #Operands used for Link or Syscall Insts 'R31': ('IntReg', 'uw','31','IsInteger', 4), 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), #Special Integer Reg operands 'HI': ('IntReg', 'uw','32', 'IsInteger', 6), 'LO': ('IntReg', 'uw','33', 'IsInteger', 7), #Immediate Value operand 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), #Floating Point Reg Operands 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2), 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), #Special Floating Point Control Reg Operands 'FIR': ('FloatReg', 'uw', '32', 'IsFloating', 1), 'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2), 'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3), 'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3), 'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3), #Operands For Paired Singles FP Operations 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4), 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5), 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5), 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6), 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6), 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), #Program Counter Operands 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4) }};