// -*- mode:c++ -*- // Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved // This software is part of the M5 simulator. // THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING // DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING // TO THESE TERMS AND CONDITIONS. // Permission is granted to use, copy, create derivative works and // distribute this software and such derivative works for any purpose, // so long as (1) the copyright notice above, this grant of permission, // and the disclaimer below appear in all copies and derivative works // made, (2) the copyright notice above is augmented as appropriate to // reflect the addition of any new copyrightable work in a derivative // work (e.g., Copyright .AN) Copyright Owner), and (3) // the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any // advertising or publicity pertaining to the use or distribution of // this software without specific, written prior authorization. // THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND // DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR // OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND // NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. // IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, // INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF // ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, // THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY // IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR // STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE // POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. //Authors: Korey L. Sewell //////////////////////////////////////////////////////////////////// // // Nop // output header {{ /** * Static instruction class for no-ops. This is a leaf class. */ class Nop : public MipsStaticInst { /// Disassembly of original instruction. const std::string originalDisassembly; public: /// Constructor Nop(const std::string _originalDisassembly, MachInst _machInst) : MipsStaticInst("nop", _machInst, No_OpClass), originalDisassembly(_originalDisassembly) { flags[IsNop] = true; } ~Nop() { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; %(BasicExecDeclare)s }; }}; output decoder {{ std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s %s", "nop", originalDisassembly); } /// Helper function for decoding nops. Substitute Nop object /// for original inst passed in as arg (and delete latter). inline MipsStaticInst * makeNop(MipsStaticInst *inst) { std::string nop_str = "(" + inst->disassemble(0) + ")"; MipsStaticInst *nop = new Nop(nop_str, inst->machInst); delete inst; return nop; } }}; output exec {{ Fault Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { return NoFault; } }}; // Int & FP operate instructions use RD as dest, so check for // RD == 0 to detect nops def template RegNopCheckDecode {{ { MipsStaticInst *i = new %(class_name)s(machInst); //if (RD == 0) { //i = makeNop(i); //} return i; } }}; def template OperateNopCheckDecode {{ { MipsStaticInst *i = new %(class_name)s(machInst); //if (RD == 0) { // i = makeNop(i); //} return i; } }}; // IntImm & Memory instructions use Rt as dest, so check for // Rt == 0 to detect nops def template ImmNopCheckDecode {{ { MipsStaticInst *i = new %(class_name)s(machInst); //if (RT == 0) { // i = makeNop(i); // } return i; } }}; // Like BasicOperate format, but generates NOP if RC/FC == 31 def format BasicOperateWithNopCheck(code, *opt_args) {{ iop = InstObjParams(name, Name, 'MipsStaticInst', code, opt_args) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = OperateNopCheckDecode.subst(iop) exec_output = BasicExecute.subst(iop) }}; def format Nop() {{ decode_block = 'return new Nop(\"\",machInst);\n' }};