// -*- mode:c++ -*- // Copyright (c) 2010 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall // not be construed as granting a license to any other intellectual // property including but not limited to intellectual property relating // to a hardware implementation of the functionality of the software // licensed hereunder. You may use the software subject to the license // terms below provided that you ensure that this notice is replicated // unmodified and in its entirety in all distributions of the software, // modified or unmodified, in source code or in binary form. // // Copyright (c) 2009 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer; // redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution; // neither the name of the copyright holders nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Gabe Black 1: decode BIGTHUMB { // 16 bit thumb instructions. 0: decode TOPCODE_15_13 { 0x0, 0x1: decode TOPCODE_13_11 { 0x0: WarnUnimpl::lsl(); //immediate 0x1: WarnUnimpl::lsr(); //immediate 0x2: WarnUnimpl::asr(); //immediate 0x3: decode TOPCODE_10_9 { 0x0: WarnUnimpl::add(); //register 0x1: WarnUnimpl::sub(); //register 0x2: WarnUnimpl::add(); //3 bit immediate 0x3: WarnUnimpl::sub(); //3 bit immediate } 0x4: WarnUnimpl::mov(); //immediate 0x5: WarnUnimpl::cmp(); //immediate 0x6: WarnUnimpl::add(); //8 bit immediate, thumb 0x7: WarnUnimpl::sub(); //8 bit immediate, thumb } 0x2: decode TOPCODE_12_10 { // Data processing 0x0: decode TOPCODE_9_6 { 0x0: WarnUnimpl::and(); //register 0x1: WarnUnimpl::eor(); //register 0x2: WarnUnimpl::lsl(); //register 0x3: WarnUnimpl::lsr(); //register 0x4: WarnUnimpl::asr(); //register 0x5: WarnUnimpl::adc(); //register 0x6: WarnUnimpl::sbc(); //register 0x7: WarnUnimpl::ror(); //register 0x8: WarnUnimpl::tst(); //register 0x9: WarnUnimpl::rsb(); //immediate 0xa: WarnUnimpl::cmp(); //register (high registers) 0xb: WarnUnimpl::cmn(); //register 0xc: WarnUnimpl::orr(); //register 0xd: WarnUnimpl::mul(); 0xe: WarnUnimpl::bic(); //register 0xf: WarnUnimpl::mvn(); //register } // Special data instructions and branch and exchange 0x1: decode TOPCODE_9_6 { 0x0: WarnUnimpl::add(); //register (low registers) 0x1, 0x2, 0x3: WarnUnimpl::add(); //register (high registers) 0x4: WarnUnimpl::unpredictable(); //? 0x5, 0x6, 0x7: WarnUnimpl::cmp(); //register 0x8: WarnUnimpl::mov(); //register (low registers) 0x9, 0xa, 0xb: WarnUnimpl::mov(); //register (high registers) 0xc, 0xd: WarnUnimpl::bx(); 0xe, 0xf: WarnUnimpl::blx(); //register } 0x2, 0x3: WarnUnimpl::ldr(); default: decode TOPCODE_11_9 { 0x0: WarnUnimpl::str(); //register 0x1: WarnUnimpl::strh(); //register 0x2: WarnUnimpl::strb(); //register 0x3: WarnUnimpl::ldrsb(); //register 0x4: WarnUnimpl::ldr(); //register 0x5: WarnUnimpl::ldrh(); //register 0x6: WarnUnimpl::ldrb(); //register 0x7: WarnUnimpl::ldrsh(); //register } } 0x3: decode TOPCODE_12_11 { 0x0: WarnUnimpl::str(); //immediate, thumb 0x1: WarnUnimpl::ldr(); //immediate, thumb 0x2: WarnUnimpl::strb(); //immediate, thumb 0x3: WarnUnimpl::ldrb(); //immediate, thumb } 0x4: decode TOPCODE_12_11 { 0x0: WarnUnimpl::strh(); //immediate, thumb 0x1: WarnUnimpl::ldrh(); //immediate, thumb 0x2: WarnUnimpl::str(); //immediate, thumb 0x3: WarnUnimpl::ldr(); //immediate, thumb } 0x5: decode TOPCODE_12_11 { 0x0: WarnUnimpl::adr(); 0x1: WarnUnimpl::add(); //sp, immediate 0x2: decode TOPCODE_10_8 { 0x0: decode TOPCODE_7 { 0x0: WarnUnimpl::add(); //sp, immediate 0x1: WarnUnimpl::sub(); //sp, immediate } 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 0x2: decode TOPCODE_7_6 { 0x0: WarnUnimpl::sxth(); 0x1: WarnUnimpl::sxtb(); 0x2: WarnUnimpl::uxth(); 0x3: WarnUnimpl::uxtb(); } 0x4, 0x5: WarnUnimpl::pop(); 0x6: decode TOPCODE_7_5 { 0x2: WarnUnimpl::setend(); 0x3: WarnUnimpl::cps(); } } 0x3: decode TOPCODE_10_8 { 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 0x2: decode TOPCODE_7_6 { 0x0: WarnUnimpl::rev(); 0x1: WarnUnimpl::rev16(); 0x3: WarnUnimpl::revsh(); } 0x4, 0x5: WarnUnimpl::pop(); 0x6: WarnUnimpl::bkpt(); 0x7: decode TOPCODE_3_0 { 0x0: WarnUnimpl::it(); default: decode TOPCODE_7_4 { 0x0: WarnUnimpl::nop(); 0x1: WarnUnimpl::yield(); 0x2: WarnUnimpl::wfe(); 0x3: WarnUnimpl::wfi(); 0x4: WarnUnimpl::sev(); default: WarnUnimpl::unallocated_hint(); } } } } 0x6: decode TOPCODE_12_11 { 0x0: WarnUnimpl::stm(); // also stmia, stmea 0x1: WarnUnimpl::ldm(); // also ldmia, ldmea default: decode TOPCODE_11_8 { 0xe: WarnUnimpl::undefined(); // permanently undefined 0xf: WarnUnimpl::svc(); // formerly swi default: WarnUnimpl::b(); // conditional } } 0x7: decode TOPCODE_12_11 { 0x0: WarnUnimpl::b(); // unconditional } } // 32 bit thumb instructions. 1: decode HTOPCODE_12_11 { 0x1: decode HTOPCODE_10_9 { 0x0: decode HTOPCODE_8_6 { 0x0, 0x6: decode HTOPCODE_4 { 0x0: WarnUnimpl::srs(); 0x1: WarnUnimpl::rfe(); } 0x1: decode HTOPCODE_5_4 { 0x0: WarnUnimpl::strex(); 0x1: WarnUnimpl::ldrex(); 0x2: WarnUnimpl::strd(); // immediate 0x3: decode HTRN { 0xf: WarnUnimpl::ldrd(); // literal default: WarnUnimpl::ldrd(); // immediate } } 0x2: decode HTOPCODE_4 { 0x0: WarnUnimpl::stm(); // stmia, stmea 0x1: decode HTRN { 0xd: WarnUnimpl::pop(); default: WarnUnimpl::ldm(); // ldmia, ldmfd } } 0x3: decode HTOPCODE_5_4 { 0x0: decode LTOPCODE_7_4 { 0x4: WarnUnimpl::strexb(); 0x5: WarnUnimpl::strexh(); 0x7: WarnUnimpl::strexd(); } 0x1: decode LTOPCODE_7_4 { 0x0: WarnUnimpl::tbb(); 0x1: WarnUnimpl::tbh(); 0x4: WarnUnimpl::ldrexb(); 0x5: WarnUnimpl::ldrexh(); 0x7: WarnUnimpl::ldrexd(); } 0x2: WarnUnimpl::strd(); // immediate 0x3: decode HTRN { 0xf: WarnUnimpl::ldrd(); // literal default: WarnUnimpl::ldrd(); // immediate } } 0x4: decode HTOPCODE_4 { 0x0: decode HTRN { 0xd: WarnUnimpl::push(); default: WarnUnimpl::stmdb(); // stmfd } 0x1: WarnUnimpl::ldmdb(); // ldmea } 0x5, 0x7: decode HTOPCODE_4 { 0x0: WarnUnimpl::strd(); // immediate 0x1: decode HTRN { 0xf: WarnUnimpl::ldrd(); // literal default: WarnUnimpl::ldrd(); // immediate } } } 0x1: decode HTOPCODE_8_5 { 0x0: decode LTRD { 0xf: decode HTS { 0x1: WarnUnimpl::tst(); // register } default: WarnUnimpl::and(); // register } 0x1: WarnUnimpl::bic(); // register 0x2: decode HTRN { 0xf: WarnUnimpl::mov(); // register default: WarnUnimpl::orr(); // register } 0x3: decode HTRN { 0xf: WarnUnimpl::mvn(); // register default: WarnUnimpl::orn(); // register } 0x4: decode LTRD { 0xf: decode HTS { 0x1: WarnUnimpl::teq(); // register } default: WarnUnimpl::eor(); // register } 0x6: WarnUnimpl::pkh(); 0x8: decode LTRD { 0xf: decode HTS { 0x1: WarnUnimpl::cmn(); // register } default: WarnUnimpl::add(); // register } 0xa: WarnUnimpl::adc(); // register 0xb: WarnUnimpl::sbc(); // register 0xd: decode LTRD { 0xf: decode HTS { 0x1: WarnUnimpl::cmp(); // register } default: WarnUnimpl::sub(); // register } 0xe: WarnUnimpl::rsb(); // register } default: decode HTOPCODE_9_8 { 0x2: decode LTOPCODE_4 { 0x0: decode LTCOPROC { 0xa, 0xb: decode OPCODE_23_20 { ##include "vfp.isa" } default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); default: decode HTOPCODE_4 { 0x0: WarnUnimpl::mcr(); // mcr2 0x1: WarnUnimpl::mrc(); // mrc2 } } } 0x3: WarnUnimpl::Advanced_SIMD(); default: decode LTCOPROC { 0xa, 0xb: decode HTOPCODE_9_4 { 0x00: WarnUnimpl::undefined(); 0x04: WarnUnimpl::mcrr(); // mcrr2 0x05: WarnUnimpl::mrrc(); // mrrc2 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: WarnUnimpl::stc(); // stc2 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: decode HTRN { 0xf: WarnUnimpl::ldc(); // ldc2 (literal) default: WarnUnimpl::ldc(); // ldc2 (immediate) } } default: decode HTOPCODE_9_5 { 0x00: WarnUnimpl::undefined(); 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: WarnUnimpl::Extension_register_load_store_instruction(); } } } } 0x2: decode LTOPCODE_15 { 0x0: decode HTOPCODE_9 { 0x0: decode HTOPCODE_8_5 { 0x0: decode LTRD { 0xf: decode HTS { 0x1: DataModImmOp::tst({{ resTemp = Rn & rotated_imm; }}); } default: DataModImmOp::and({{ Rs = resTemp = Rn & rotated_imm; }}); } 0x1: DataModImmOp::bic({{ Rs = resTemp = Rn & ~rotated_imm; }}); 0x2: decode HTRN { 0xf: DataModImmOp::mov({{ Rs = resTemp = rotated_imm; }}); default: DataModImmOp::orr({{ Rs = resTemp = Rn | rotated_imm; }}); } 0x3: decode HTRN { 0xf: DataModImmOp::mvn({{ Rs = resTemp = ~rotated_imm; }}); default: DataModImmOp::orn({{ Rs = resTemp = Rn | ~rotated_imm; }}); } 0x4: decode LTRD { 0xf: decode HTS { 0x1: DataModImmOp::teq({{ resTemp = Rn ^ rotated_imm; }}); } default: DataModImmOp::eor({{ Rs = resTemp = Rn ^ rotated_imm; }}); } 0x8: decode LTRD { 0xf: decode HTS { 0x1: DataModImmOp::cmn({{ resTemp = Rn + rotated_imm; }}, add); } default: DataModImmOp::add({{ Rs = resTemp = Rn + rotated_imm; }}, add); } 0xa: DataModImmOp::adc({{ Rs = resTemp = Rn + rotated_imm + CondCodes<29:>; }}, add); 0xb: DataModImmOp::sbc({{ Rs = resTemp = Rn - rotated_imm - !CondCodes<29:>; }}, sub); 0xd: decode LTRD { 0xf: decode HTS { 0x1: DataModImmOp::cmp({{ resTemp = Rn - rotated_imm; }}, sub); } default: DataModImmOp::sub({{ Rs = resTemp = Rn - rotated_imm; }}, sub); } 0xe: DataModImmOp::rsb({{ Rs = resTemp = rotated_imm - Rn; }}, rsb); } 0x1: WarnUnimpl::Data_processing_plain_binary_immediate(); } 0x1: WarnUnimpl::Branches_and_miscellaneous_control(); } 0x3: decode HTOPCODE_10_9 { 0x0: decode HTOPCODE_4 { 0x0: decode HTOPCODE_8 { 0x0: Thumb32StoreSingle::thumb32StoreSingle(); 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store(); } 0x1: decode HTOPCODE_6_5 { 0x0: WarnUnimpl::Load_byte_memory_hints(); 0x1: WarnUnimpl::Load_halfword_memory_hints(); 0x2: Thumb32LoadWord::thumb32LoadWord(); 0x3: WarnUnimpl::undefined(); } } 0x1: decode HTOPCODE_8_7 { 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference(); 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide(); default: WarnUnimpl::Data_processing_register(); } default: decode HTOPCODE_9_8 { 0x2: decode LTOPCODE_4 { 0x0: decode LTCOPROC { 0xa, 0xb: WarnUnimpl::VFP_Inst(); default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); default: decode HTOPCODE_4 { 0x0: WarnUnimpl::mcr(); // mcr2 0x1: WarnUnimpl::mrc(); // mrc2 } } } 0x3: WarnUnimpl::Advanced_SIMD(); default: decode LTCOPROC { 0xa, 0xb: decode HTOPCODE_9_4 { 0x00: WarnUnimpl::undefined(); 0x04: WarnUnimpl::mcrr(); // mcrr2 0x05: WarnUnimpl::mrrc(); // mrrc2 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: WarnUnimpl::stc(); // stc2 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: decode HTRN { 0xf: WarnUnimpl::ldc(); // ldc2 (literal) default: WarnUnimpl::ldc(); // ldc2 (immediate) } } default: decode HTOPCODE_9_5 { 0x00: WarnUnimpl::undefined(); 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: WarnUnimpl::Extension_register_load_store_instruction(); } } } } } }