// -*- mode:c++ -*- // Copyright (c) 2010 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall // not be construed as granting a license to any other intellectual // property including but not limited to intellectual property relating // to a hardware implementation of the functionality of the software // licensed hereunder. You may use the software subject to the license // terms below provided that you ensure that this notice is replicated // unmodified and in its entirety in all distributions of the software, // modified or unmodified, in source code or in binary form. // // Copyright (c) 2007-2008 The Florida State University // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer; // redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution; // neither the name of the copyright holders nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Stephen Hines //////////////////////////////////////////////////////////////////// // // The actual ARM ISA decoder // -------------------------- // The following instructions are specified in the ARM ISA // Specification. Decoding closely follows the style specified // in the ARM ISA specification document starting with Table B.1 or 3-1 // // 0: decode COND_CODE { 0xF: ArmUnconditional::armUnconditional(); default: decode ENCODING { format DataOp { 0x0: decode SEVEN_AND_FOUR { 1: decode MISC_OPCODE { 0x9: decode PREPOST { 0: ArmMultAndMultAcc::armMultAndMultAcc(); 1: ArmSyncMem::armSyncMem(); } 0xb, 0xd, 0xf: AddrMode3::addrMode3(); } 0: decode IS_MISC { 0: ArmDataProcReg::armDataProcReg(); 1: decode OPCODE_7 { 0x0: decode MISC_OPCODE { 0x0: ArmMsrMrs::armMsrMrs(); 0x1: ArmBxClz::armBxClz(); 0x2: decode OPCODE { 0x9: WarnUnimpl::bxj(); } 0x3: decode OPCODE { 0x9: ArmBlxReg::armBlxReg(); } 0x5: ArmSatAddSub::armSatAddSub(); } 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); } } } 0x1: decode IS_MISC { 0: ArmDataProcImm::armDataProcImm(); 1: decode OPCODE { // The following two instructions aren't supposed to be defined 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 0x9: decode RN { 0: decode IMM { 0: PredImmOp::nop({{ ; }}); 1: WarnUnimpl::yield(); 2: WarnUnimpl::wfe(); 3: WarnUnimpl::wfi(); 4: WarnUnimpl::sev(); } default: PredImmOp::msr_i_cpsr({{ uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, rotated_imm, RN, false); Cpsr = ~CondCodesMask & newCpsr; CondCodes = CondCodesMask & newCpsr; }}); } 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 0xb: PredImmOp::msr_i_spsr({{ Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); }}); } } 0x2: AddrMode2::addrMode2(True); 0x3: decode OPCODE_4 { 0: AddrMode2::addrMode2(False); 1: decode OPCODE_24_23 { 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 0x2: ArmSignedMultiplies::armSignedMultiplies(); 0x3: ArmMiscMedia::armMiscMedia(); } } 0x4: ArmMacroMem::armMacroMem(); 0x5: decode OPCODE_24 { 0: ArmBBlxImm::armBBlxImm(); 1: ArmBlBlxImm::armBlBlxImm(); } 0x6: decode CPNUM { 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); } 0x7: decode OPCODE_24 { 0: decode OPCODE_4 { 0: decode CPNUM { 0xa, 0xb: decode OPCODE_23_20 { ##include "vfp.isa" } } // CPNUM 1: decode CPNUM { // 27-24=1110,4 ==1 1: decode OPCODE_15_12 { format FloatOp { 0xf: decode OPCODE_23_21 { format FloatCmp { 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); } } default: decode OPCODE_23_20 { 0x0: decode OPCODE_7 { 0: flts({{ Fn.sf = (float) Rd.sw; }}); 1: fltd({{ Fn.df = (double) Rd.sw; }}); } 0x1: decode OPCODE_7 { 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 1: fixd({{ Rd = (uint32_t) Fm.df; }}); } 0x2: wfs({{ Fpsr = Rd; }}); 0x3: rfs({{ Rd = Fpsr; }}); 0x4: FailUnimpl::wfc(); 0x5: FailUnimpl::rfc(); } } // format FloatOp } 0xa: decode MISC_OPCODE { 0x1: decode MEDIA_OPCODE { 0xf: decode RN { 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); } 0xe: decode RN { 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); } } // MEDIA_OPCODE (MISC_OPCODE 0x1) } // MISC_OPCODE (CPNUM 0xA) 0xf: McrMrc15::mcrMrc15(); } // CPNUM (OP4 == 1) } //OPCODE_4 1: Svc::svc(); } // OPCODE_24 } } }