Lines Matching refs:r31
156 br r31, 2f; \
202 lda _rid, 7(r31); /* IOP7 */ \
203 br r31, 6f; \
206 lda _rid, 6(r31); /* IOP6 */ \
207 br r31, 6f; \
210 lda _rid, 5(r31); /* IOP5 */ \
211 br r31, 6f; \
214 lda r14, 4(r31); /* IOP4 */ \
215 br r31, 6f; \
216 5: lda r14, 0(r31); /* passive release */ \
291 bis r31, 0x1, r16 // get a one
302 lda r16,0xf01(r31)
304 ldah r13,0xa0(r31)
309 lda r13, 0xff8e(r31) // Load the upper address bits
342 // #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
344 lda r13, 0x10(r31) // assume 16Mbytes of cache
351 or r31, 8192/(32*8), r13 // get count of loads
358 ldq_p r31, 32*0(r12) // do a load
359 ldq_p r31, 32*1(r12) // do next load
361 ldq_p r31, 32*2(r12) // do next load
362 ldq_p r31, 32*3(r12) // do next load
364 ldq_p r31, 32*4(r12) // do next load
365 ldq_p r31, 32*5(r12) // do next load
367 ldq_p r31, 32*6(r12) // do next load
368 ldq_p r31, 32*7(r12) // do next load
387 mfpr r31, pt0 // Pad exc_addr write
427 or r31, r31, r0
455 lda r0,17(r31) // bogus
463 lda r0, hlt_c_callback(r31)
464 br r31, sys_enter_console
477 addq r31, 64, r0 // initialize loop counter
493 addq r31, 48, r0 // initialize loop counter
506 or r31, 1, r0 // set success
547 br r31, pal_pal_bug_check_from_int
575 or r31,0,r16 // IPI interrupt A0 = 0
576 lda r12,0xf01(r31) // build up an address for the MISC register
584 or r31,0x1,r14 // load r14 with bit to clear
589 br r31, pal_post_interrupt // Notify the OS
594 or r31,1,r16 // a0 means it is a clock interrupt
595 lda r12,0xf01(r31) // build up an address for the MISC register
603 or r31,0x1,r14 // load r14 with bit to clear
608 br r31, pal_post_interrupt // Tell the OS
629 br r31, pal_post_dev_interrupt //
631 1: lda r16, osfint_c_passrel(r31) // passive release
632 br r31, pal_post_interrupt //
638 lda r12,0xf01(r31) // calculate DIRn address
640 ldah r13,DIR_addr(r31)
658 lda r13,0x280(r31)
666 or r31,1,r14 // set bit 55 (ISA Interrupt)
670 lda r16,0x900(r31) // load offset for normal into r13
673 lda r16,0x800(r31) // replace with offset for pic
674 lda r12,0xf01(r31) // build an addr to access PIC
676 ldah r13,0xfc(r31)
688 lda r10,63(r31)
691 lda r13,0x10(r31)
695 or r31,3,r16 // a0 means it is a I/O interrupt
697 br r31, pal_post_interrupt
714 1: lda r16, osfint_c_passrel(r31) // passive release
715 br r31, pal_post_interrupt //
742 br r31, pal_post_dev_interrupt //
744 1: lda r16, osfint_c_passrel(r31) // passive release
745 br r31, pal_post_interrupt //
766 br r31, pal_post_dev_interrupt //
768 1: lda r16, osfint_c_passrel(r31) // passive release
769 br r31, pal_post_interrupt //
774 lda r13, 1(r31) // Duart0 bit
795 br r31, pal_post_dev_interrupt //
796 1: lda r16, osfint_c_passrel(r31) // passive release
797 br r31, pal_post_interrupt //
802 lda r13, 0xffb(r31) // get upper GBUS address bits
808 lda r13, 0x40(r31) // load Intim bit
811 lda r16, osfint_c_clk(r31) // passive release
812 br r31, pal_post_interrupt // Build the stack frame
817 lda r13, 0x20(r31) // load IP Int bit
820 lda r16, osfint_c_ip(r31) // passive release
821 br r31, pal_post_interrupt // Build the stack frame
826 lda r13, 0xffa(r31) // get upper GBUS address bits
830 lda r14, 3(r31) // index to RR3
850 lda r8, 0(r31) // passive release
851 br r31, clear_duart0_int // clear tlintrsum and post
856 lda r8, 0x680(r31) // UART0 RX vector
857 br r31, clear_duart0_int // clear tlintrsum and post
862 lda r14, 0x28(r31) // Reset TX Int Pending code
867 lda r8, 0x6c0(r31) // UART0 TX vector
868 br r31, clear_duart0_int // clear tlintrsum and post
873 lda r8, 0x690(r31) // UART1 RX vector
874 br r31, clear_duart0_int // clear tlintrsum and post
879 lda r14, 0x28(r31) // Reset TX Int Pending code
882 lda r8, 0x6d0(r31) // UART1 TX vector
883 br r31, clear_duart0_int // clear tlintrsum and post
888 lda r13, 1(r31) // load duart0 bit
892 or r8, r31, r13 // move vector to r13
893 br r31, pal_post_dev_interrupt // Build the stack frame
897 // lda r16, osfint_c_passrel(r31) // passive release
898 // br r31, pal_post_interrupt //
915 ornot r31, r31, r12 // set flag
916 lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code
917 br r31, sys_merge_sys_corr // jump to CRD logout frame code
919 1: lda r16, osfint_c_passrel(r31) // passive release
925 or r13, r31, r17 // move vector to a1
926 or r31, osfint_c_dev, r16 // a0 signals IO device interrupt
948 mfpr r31, pt0 // Pad write to dtb_cm
962 lda r12, 0xffc4(r31) // get GBUS_MISCR address bits
969 lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
971 lda r14, 0x40(r31) // get bit <6> mask
978 1: br r31, sys_int_mchk // do a machine check
980 lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector
983 lda r16, osfint_c_dev(r31) // a0 to device code
999 ldah r13, 0x1800(r31) // load Halt/^PHalt bits
1006 lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt
1007 br r31, sys_enter_console // enter the console
1036 lda r9, 1(r31)
1040 or r31, r31, r12 // clear flag
1041 lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code
1044 ldah r14, 0xfff0(r31)
1051 bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub
1060 or r8, r31, r12 // Must only be executed once in this flow, and must
1061 br r31, 2f // be after the scrub routine.
1071 or r13, r31, r14 // don't set SCE if disabled
1072 br r31, 8f // continue
1074 br r31, 8f
1078 or r13, r31, r14 // don't set PCE if disabled
1079 br r31, 8f // continue
1096 lda r1, 3(r31) // Set retry and 2nd error flags
1113 lda r1, 1(r31) // Set retry flag
1129 lda r1, 0xffc4(r31) // Get GBUS$MISCR address
1155 br r31, 6f
1167 br r31, sys_crd_dismiss_interrupt // just return
1176 lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
1177 lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector
1180 lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector
1182 1: subq r31, 1, r18 // get a -1
1199 br r31, Call_Pal_Rti
1230 lda r8, 0x20(r31) // flip bit 5 to touch next hexaword
1247 lda r8, 0x20(r31) // restore r0 to original address
1254 1: ret r31, (r13) // and back we go
1276 lda r14, mchk_c_sys_hrd_error(r31)
1292 lda r14, scb_v_sysmchk(r31) // Get SCB vector
1300 ldah r14, 0xfff0(r31)
1309 br r31, sys_mchk_collect_iprs // Join common machine check flow
1331 lda r17, scb_v_perfmon(r31) // a1 to interrupt vector
1334 lda r16, osfint_c_perf(r31) // a0 to perf counter code
1339 or r31, r31, r18 // assume interrupt was pc0
1347 lda r25, 1(r31) // get a one
1380 // mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load
1381 mtpr r31, itb_ia // clear the ITB
1382 mtpr r31, dtb_ia // clear the DTB
1388 mtpr r31, astrr // stop ASTs
1389 mtpr r31, aster // stop ASTs
1390 mtpr r31, sirr // clear software interrupts
1396 bis r31, 1, r0
1407 lda r1, BIT(dc_mode_v_dc_ena)(r31)
1412 mfpr r31, pt0 // No Mbox instr in 1,2,3,4
1413 mfpr r31, pt0
1414 mfpr r31, pt0
1415 mfpr r31, pt0
1416 mtpr r31, dc_flush // flush Dcache
1419 lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
1420 lda r1, 0x1F(r31)
1422 mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy
1423 mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy
1438 ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
1448 mtpr r31, exc_sum // clear out exeception summary and exc_mask
1449 mfpr r31, va // unlock va, mmstat
1453 lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
1458 mtpr r31, pt_trap
1466 mtpr r31, dtb_asn
1467 mtpr r31, itb_asn
1469 lda r1, 0x67(r31)
1473 lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
1483 or r31, 1, r9 // get a one
1485 mtpr r31, cc // clear Cycle Counter
1487 mtpr r31, pt_scc // clear System Cycle Counter
1491 mtpr r31, maf_mode // no mbox instructions for 3 cycles
1492 or r31, 1, r1 // get bogus scbb value
1494 mtpr r31, pt_prbr // clear out prbr
1500 br r31, kludge_initial_pcbb
1513 lda r1, 2(r31) // get a two
1517 mtpr r31, pt_ptbr
1519 mtpr r31, pmctr
1524 ldah r14, 0xfff0(r31)
1527 stq_p r31, 0(r13) // Clear lock_flag
1530 br r31, sys_enter_console // enter the cosole
1539 or r31, 1, r9
1570 lda r24, 1(r31)
1582 or r31, r31, r0 // set success
1584 mfpr r31, pt0 // stall
1624 lda r0, scb_v_procmchk(r31) // SCB vector
1636 lda r0, mchk_c_proc_hrd_error(r31) // MCHK code
1644 ldah r14, 0xfff0(r31)
1652 mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed.
1662 lda r4, 0xffc4(r31) // get GBUS$MISCR address bits
1668 lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits
1670 lda r6, 0x40(r31) // get bit <6> mask
1703 mtpr r31, dc_flush // Flush the Dcache
1705 mfpr r31, pt0 // Pad Mbox instructions from dc_flush
1706 mfpr r31, pt0
1711 bis r9, r31, r31 // Touch ld to make sure it completes before
1718 bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
1719 bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT
1721 ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked
1735 bis r31, r31, r5 // Clear local retryable flag
1738 lda r4, 1(r31)
1746 lda r4, 1(r31)
1752 bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control
1758 // bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
1759 bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
1761 // bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
1762 bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
1766 lda r4, 7(r31)
1771 lda r4, 0x7f8(r31)
1798 lda r4, 3(r31)
1804 lda r4, 0x7f8(r31)
1814 bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
1862 lda r4, mchk_sys_base(r31) // sys offset
1888 ldah r13, 0xfff0(r31)
1903 ldah r13, 0xfff0(r31)
1909 lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
1912 lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31)
1916 GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value
1919 lda r0, mchk_c_retryable_ird(r31) // set new MCHK code
1920 br r31, do_670 // setup new vector
1923 GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value
1926 lda r0, mchk_c_dcperr(r31) // set new MCHK code
1927 br r31, do_670 // setup new vector
1930 GET_ADDR(r0,0x107ff,r31) // get SC_STAT value
1933 lda r0, mchk_c_scperr(r31) // set new MCHK code
1934 br r31, do_670 // setup new vector
1937 GET_ADDR(r0,0x30000000,r31) // get EI_STAT value
1940 lda r0, mchk_c_bcperr(r31) // set new MCHK code
1941 br r31, do_670 // setup new vector
1944 GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value
1946 GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
1950 GET_ADDR(r0, 0xfff0, r31) // set new MCHK code
1951 br r31, do_660 // setup new vector
1954 GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value
1957 GET_ADDR(r0, 0xfffa, r31) // set new MCHK code
1958 br r31, do_660 // setup new vector
1961 GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value
1964 GET_ADDR(r0, 0xfffb, r31) // set new MCHK code
1965 br r31, do_660 // setup new vector
1968 GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value
1971 GET_ADDR(r0, 0xfffc, r31) // set new MCHK code
1972 br r31, do_660 // setup new vector
1975 GET_ADDR(r0,0xb,r31) // get EI_STAT mask value
1979 GET_ADDR(r0,0xfffd,r31) // set new MCHK code
1980 br r31, do_660 // setup new vector
1983 GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value
1986 GET_ADDR(r0, 0xfffe, r31) // set new MCHK code
1987 br r31, do_660 // setup new vector
1989 do_670: lda r8, scb_v_procmchk(r31) // SCB vector
1990 br r31, do_6x0_cont
1991 do_660: lda r8, scb_v_sysmchk(r31) // SCB vector
1995 GET_ADDR(r4,0xffff, r31) // mask for vector field
2014 mtpr r31, exc_sum // Clear Exception Summary
2029 bis r14, r31, r12 // stash pointer to logout area
2035 mtpr r31, dtb_cm
2036 mtpr r31, ev5__ps
2052 lda r16, osfint_c_mchk(r31) // flag as mchk in a0
2060 or r31, 7, r11 // get new ps (km, high ipl)
2061 subq r31, 1, r18 // get a -1
2064 bis r31, ipl_machine_check, r25
2082 lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
2083 lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector
2085 subq r31, 1, r18 // get a -1
2101 br r31, sys_mchk_write_logout_frame //
2114 lda r0, hlt_c_dbl_mchk(r31)
2115 br r31, sys_enter_console
2126 lda r0, hlt_c_mchk_from_pal(r31)
2127 br r31, sys_enter_console
2154 ret r31, (r12) // return if no outstanding arithmetic error
2157 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel
2164 bis r11, r31, r25 // save ps
2167 bis r31, r31, r25 // set the new ps
2175 mtpr r31, ev5__ps // Set Ibox current mode to kernel
2186 bis r13, r31, r16 // move exc_sum to r16
2193 bis r25, r31, r11 // set new ps
2199 ret r31, (r12) // return if no outstanding arithmetic error
2238 subq r31, 1, r1
2275 rc r31 // clear intr_flag
2337 ret r31, (r10) // return to where we came from