Lines Matching refs:r13
239 OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
261 OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
263 OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
265 OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
269 and r13, 0xf, r25; /* isolate low 4 bits */ \
279 bic r13, 0xf, r13 /* clear low 4 bits of vector */
304 ldah r13,0xa0(r31)
305 sll r13,8,r13
306 bis r16,r13,r16
309 lda r13, 0xff8e(r31) // Load the upper address bits
310 sll r13, 24, r13 // shift them to the top
319 stq_p r14, 0x40(r13) // Write to TLIPINTR reg
342 // #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
344 lda r13, 0x10(r31) // assume 16Mbytes of cache
345 sll r13, 20, r13 // convert to bytes
349 xor r12, r13, r12 // xor addr<18>
351 or r31, 8192/(32*8), r13 // get count of loads
355 subq r13, 1, r13 // decr counter
376 bne r13, cflush_loop // loop till done
518 // r13 - INTID (new EV5 IPL)
524 cmpeq r13, 31, r12 // Check for level 31 interrupt
527 cmpeq r13, 30, r12 // Check for level 30 interrupt
530 cmpeq r13, 29, r12 // Check for level 29 interrupt
533 cmpeq r13, 23, r12 // Check for level 23 interrupt
536 cmpeq r13, 22, r12 // Check for level 22 interrupt
539 cmpeq r13, 21, r12 // Check for level 21 interrupt
542 cmpeq r13, 20, r12 // Check for level 20 interrupt
561 // r13 - INTID (new EV5 IPL)
613 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
614 srl r13, 12, r13 // shift down to examine IPL15
616 Intr_Find_TIOP(r13,r14)
622 ldl_p r13, 0(r10) // Read the TLILID register
623 bne r13, pal_post_dev_interrupt
624 beq r13, 1f
626 and r13, 0x3, r10 // check for PCIA bits
640 ldah r13,DIR_addr(r31)
641 sll r13,8,r13
642 bis r12,r13,r12
644 mfpr r13, pt_whami // get CPU ID
645 extbl r13, 1, r13 // Isolate just whami bits
648 sll r13,4,r13
649 or r12,r13,r12
652 and r13,0x1,r14 // grab LSB and shift left 6
654 and r13,0x2,r10 // grabl LSB+1 and shift left 9
658 lda r13,0x280(r31)
659 bis r12,r13,r12
664 ldq_p r13, 0(r12) // read DIRn
669 and r13, r14, r14 // check if bit 55 is set
670 lda r16,0x900(r31) // load offset for normal into r13
676 ldah r13,0xfc(r31)
677 sll r13,8,r13
678 bis r12,r13,r12
679 ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev
682 //ctlz r13,r14 // count the number of leading zeros
691 lda r13,0x10(r31)
692 mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit)
702 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
703 srl r13, 22, r13 // shift down to examine IPL17
705 Intr_Find_TIOP(r13,r14)
711 ldl_p r13, 0(r10) // Read the TLILID register
712 bne r13, pal_post_dev_interrupt
720 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
721 srl r13, 6, r14 // check the Intim bit
724 srl r13, 5, r14 // check the IP Int bit
727 srl r13, 17, r13 // shift down to examine IPL16
729 Intr_Find_TIOP(r13,r14)
735 ldl_p r13, 0(r10) // Read the TLILID register
736 bne r13, pal_post_dev_interrupt
737 beq r13, 1f
739 and r13, 0x3, r10 // check for PCIA bits
750 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
751 srl r13, 12, r13 // shift down to examine IPL15
753 Intr_Find_TIOP(r13,r14)
759 ldl_p r13, 0(r10) // Read the TLILID register
760 bne r13, pal_post_dev_interrupt
761 beq r13, 1f
763 and r13, 0x3, r10 // check for PCIA bits
774 lda r13, 1(r31) // Duart0 bit
775 Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
777 Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
778 blbs r13, tlep_uart0 // go service UART int
780 srl r13, 7, r13 // shift down to examine IPL14
781 Intr_Find_TIOP(r13,r14)
787 ldl_p r13, 0(r10) // Read the TLILID register
789 bne r13, pal_post_dev_interrupt
790 beq r13, 1f
792 and r13, 0x3, r10 // check for PCIA bits
802 lda r13, 0xffb(r31) // get upper GBUS address bits
803 sll r13, 28, r13 // shift up to top
805 lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset)
806 ldq_p r13, 0(r13) // read CSRC
808 lda r13, 0x40(r31) // load Intim bit
809 Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit
817 lda r13, 0x20(r31) // load IP Int bit
818 Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit
826 lda r13, 0xffa(r31) // get upper GBUS address bits
827 sll r13, 28, r13 // shift up to top
829 ldl_p r14, 0x80(r13) // zero pointer register
832 stl_p r14, 0x80(r13) // write pointer register
836 ldl_p r14, 0x80(r13) // read RR3
864 stl_p r14, 0x80(r13) // write Channel A WR0
880 stl_p r14, 0(r13) // write Channel B WR0
888 lda r13, 1(r31) // load duart0 bit
889 Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
892 or r8, r31, r13 // move vector to r13
909 ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset
910 srl r13, 17, r13 // shift down the CWDE/CRDE bits
912 and r13, 3, r13 // mask the CWDE/CRDE bits
913 beq r13, 1f
925 or r13, r31, r17 // move vector to a1
969 lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
970 sll r13, 24, r13 // shift to proper position
972 ldq_p r12, 0(r13) // read GBUS$SERNUM
974 stq_p r14, 0(r13) // clear GBUS$SERNUM<6>
999 ldah r13, 0x1800(r31) // load Halt/^PHalt bits
1000 Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits
1018 // r13 - INTID (new EV5 IPL)
1033 srl r25, isr_v_crd, r13 //Check for CRD
1034 blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!!
1055 bsr r13, sys_crd_scrub_mem // and go scrub
1066 2: mfpr r13, pt_mces // Get MCES
1069 srl r13, mces_v_dsc, r14 // check if 620 reporting disabled
1071 or r13, r31, r14 // don't set SCE if disabled
1073 5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit
1076 6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled
1078 or r13, r31, r14 // don't set PCE if disabled
1080 7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit
1084 srl r13, mces_v_sce, r1 // Get SCE
1085 srl r13, mces_v_pce, r14 // Get PCE
1154 srl r13, mces_v_dsc, r10 // logging enabled?
1156 5: srl r13, mces_v_dpc, r10 // logging enabled?
1161 GET_IMPURE(r13) // addr of per-cpu impure area
1162 GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13)
1163 ldl_p r10, mchk_crd_rsvd(r13) // bump counter
1165 stl_p r10, mchk_crd_rsvd(r13)
1254 1: ret r31, (r13) // and back we go
1526 GET_IMPURE(r13)
1527 stq_p r31, 0(r13) // Clear lock_flag
1625 mfpr r13, pt_mces // Get MCES
1627 bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
1653 blbs r13, sys_double_machine_check // MCHK halt if double machine check
1691 // r0, r1, r4, r5, r6, r12, r13, r25 - available
1716 ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR
1718 bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
1840 // r13 - bc_tag_addr
1883 stq_p r13, mchk_bc_tag_addr(r14)
1888 ldah r13, 0xfff0(r31)
1889 zapnot r13, 0x1f, r13
1890 ldq_p r13, ei_stat(r13)
1891 sll r13, 64-ei_stat_v_bc_tperr, r13
1892 srl r13, 64-ei_stat_v_bc_tperr, r13
1893 or r25, r13, r25
1903 ldah r13, 0xfff0(r31)
1904 zap r13, 0xE0, r13 // Get Cbox IPR base
1905 ldq_p r13, ld_lock(r13) // Get ld_lock IPR
1906 stq_p r13, mchk_ld_lock(r14) // and stash it in the frame
2137 // r13 - available
2149 mfpr r13, ev5__exc_sum
2150 srl r13, exc_sum_v_swc, r13
2151 bne r13, handle_arith_and_mchk
2186 bis r13, r31, r16 // move exc_sum to r16