Lines Matching refs:r31
202 mtpr r31, ev5__ps // Set Ibox current mode to kernel
204 bis r11, r31, r12 // Save PS
208 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
212 bis r31, r31, r12 // Set new PS
223 or r31, mmcsr_c_acv, r17 // pass mm_csr as a1
229 bis r12, r31, r11 // update ps
238 subq r31, 1, r18 // pass flag of istream, as a2
265 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern
288 mtpr r31, ev5__ps // Set Ibox current mode to kernel
298 bis r12, r31, r11 // set new ps
309 br r31, sys_interrupt // Go handle interrupt
340 mfpr r31, ev5__va // Unlock VA in case there was a double miss
395 mfpr r31, pt0 // Pad the write to dtb_tag
493 mtpr r31, ev5__ps // Set Ibox current mode to kernel
505 cmpeq r8, 0x1F, r8 // check for r31/F31
506 bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault
509 bis r11, r31, r12 // Save PS
513 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
517 bis r31, r31, r12 // Set new PS
543 bis r12, r31, r11 // update ps
544 br r31, unalign_trap_cont
569 mtpr r31, ev5__ps // Set Ibox current mode to kernel
577 bis r8, r31, r14 // move exc_addr to correct place
578 bis r11, r31, r12 // Save PS
580 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
587 //dismiss exception if load to r31/f31
596 cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31?
605 bis r31, r31, r12 // Set new PS
608 br r31, dfault_trap_cont
625 mtpr r31, ic_flush_ctl // Flush the Icache
626 br r31, sys_machine_check
649 mtpr r31, ev5__ps // Set Ibox current mode to kernel
654 bis r11, r31, r12 // Save PS
658 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
662 bis r31, r31, r12 // Set new PS
670 bis r31, osf_a0_opdec, r16 // set a0
681 bis r12, r31, r11 // update ps
709 mfpr r31, ev5__va // unlock mbox
711 bis r11, r31, r25 // save ps
717 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
721 bis r31, r31, r25 // set the new ps
728 mtpr r31, ev5__ps // Set Ibox current mode to kernel
740 bis r25, r31, r11 // set new ps
747 mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask
775 mtpr r31, ev5__ps // Set Ibox current mode to kernel
783 bis r11, r31, r12 // Save PS
786 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
790 bis r31, r31, r12 // Set new PS
805 bis r12, r31, r11 // set new ps
810 bis r31, osf_a0_fen, r16 // set a0
824 bis r31, osf_a0_opdec, r16 // set a0
859 bis r25, r31, r16 // a0 <- va
865 bis r12, r31, r11 // update ps
930 mfpr r31, va // unlock VA
951 mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode
952 mtpr r31, ips
957 lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt
958 br r31, sys_enter_console // enter the console
962 bis r10, r31, r14 // bugcheck expects exc_addr in r14
963 br r31, pal_pal_bug_check
967 // dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31
978 mfpr r31, va // unlock the mbox
982 mfpr r31, pt0 // pad exc_addr write
998 lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code
999 br r31, pal_pal_mchk
1016 mfpr r31, pt0 // Pad for mt->mf paltemp rule
1024 mfpr r31, pt0 // Pad for mt->mf paltemp rule
1032 mfpr r31, pt0 // Pad for mt->mf paltemp rule
1040 mfpr r31, pt0 // Pad for mt->mf paltemp rule
1048 mfpr r31, pt0 // Pad for mt->mf paltemp rule
1056 mfpr r31, pt0 // Pad for mt->mf paltemp rule
1068 mtpr r31, ev5__dtb_ia // Flush DTB
1069 mtpr r31, ev5__itb_ia // Flush ITB
1077 mtpr r31, ev5__dtb_iap // Flush DTB
1078 mtpr r31, ev5__itb_iap // Flush ITB
1113 br r31, tbi_finish
1152 mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles
1172 or r25, r31, sp // sp
1234 mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel)
1237 or r3, r31, r4
1248 or r31, r31, r0 // set status to success
1250 jmp r31, (r4) // and call our friend, it's her problem now
1277 mtpr r31, ev5__ps // Set Ibox current mode to kernel
1279 bis r11, r31, r12 // Save PS for stack write
1283 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
1287 bis r31, r31, r11 // Set new PS
1296 or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack
1300 or r14, r31, r16 // pass pc/va as a0
1306 lda r17, mmcsr_c_acv(r31) // assume ACV
1312 subq r31, 1, r18 // pass flag of istream as a2
1336 mtpr r31, ev5__ps // Set Ibox current mode to kernel
1338 bis r11, r31, r12 // Save PS for stack write
1342 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
1346 bis r31, r31, r11 // Set new PS
1355 or r10, r31, r14 // Save pc/va in case TBmiss on stack
1359 or r14, r31, r16 // pass pc/va as a0
1371 subq r31, 1, r18 // pass flag of istream as a2
1403 bis r12, r31, r14 // save PC in case of tbmiss or fault
1412 //dismiss exception if load to r31/f31
1421 cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31?
1426 mtpr r31, ev5__ps // Set Ibox current mode to kernel
1428 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
1435 bis r31, r31, r11 // Set new PS
1441 or r10, r31, r25 // Save va in case TBmiss on stack
1445 or r25, r31, r16 // pass va as a0
1448 or r31, mmcsr_c_acv, r17 // assume acv
1456 or r13, r31, r18 // pass flag of dstream access and read vs write
1473 // fetch, fetch_m, of load to r31/f31.
1484 mfpr r31, pt0 // pad exc_addr write
1513 lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set
1515 cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0
1534 br r31, ksp_inval_halt
1547 mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
1627 mtpr r31, ev5__ps // Set Ibox current mode to kernel
1632 bis r11, r31, r12 // Save PS for stack write
1636 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
1640 bis r31, r31, r11 // Set new PS
1648 bis r31, osf_a0_opdec, r16 // set a0
1686 br r31, pal_update_pcb_20_ // join common
1694 ret r31, (r0)
1743 //orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag
1744 SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag
1775 ldah r0, (1<<(icsr_v_sde-16))(r31)
1779 mfpr r31, pt0 // SDE bubble cycle 1
1780 mfpr r31, pt0 // SDE bubble cycle 2
1781 mfpr r31, pt0 // SDE bubble cycle 3
1785 // save integer regs R4-r31
1813 SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1)
1848 mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write)
1849 mfpr r31, pt0
1852 mfpr r31, pt0 // SDE bubble cycle 1
1853 mfpr r31, pt0 // SDE bubble cycle 2
1854 mfpr r31, pt0 // SDE bubble cycle 3
1937 or r31, 1, r2 // get a one
1943 mtpr r31, dtbIa // Clear all DTB entries
1959 sll r31, 0, r31 // stall cycle 1
1960 sll r31, 0, r31 // stall cycle 2
1961 sll r31, 0, r31 // stall cycle 3
2016 //orig lda r0, cns_mchksize(r31) // get size of mchk area
2022 lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area
2026 //orig or r31, 1, r0 // get a one
2032 or r31, 1, r0 // get a one
2040 mtpr r31, dtb_ia // clear the dtb
2041 mtpr r31, itb_ia // clear the itb
2044 ret r31, (r3) // and back we go
2071 mtpr r31, dtbIa // Clear all DTB entries
2095 mfpr r31, pt0 // FPE bubble cycle 1 //orig
2096 mfpr r31, pt0 // FPE bubble cycle 2 //orig
2097 mfpr r31, pt0 // FPE bubble cycle 3 //orig
2194 //orig mfpr r31, pt0 // (may issue with mt maf_mode)
2195 //orig mfpr r31, pt0 // bubble cycle 1
2196 //orig mfpr r31, pt0 // bubble cycle 2
2197 //orig mfpr r31, pt0 // bubble cycle 3
2198 //orig mfpr r31, pt0 // (may issue with following ld)
2239 mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway)
2240 mfpr r31, pt0 // ""
2242 ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location
2246 mfpr r31, pt0 // SDE bubble cycle 1
2247 mfpr r31, pt0 // SDE bubble cycle 2
2248 mfpr r31, pt0 // SDE bubble cycle 3
2288 RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1)
2302 //orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag
2307 SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag
2322 mfpr r31, pt0 // stall for ldq_p above //orig
2324 mtpr r31, dtb_ia // clear the tb //orig
2325 mtpr r31, itb_ia // clear the itb //orig
2328 ret r31, (r3) // back we go //orig
2358 lda r25, mchk_c_bugcheck(r31)
2360 br r31, pal_pal_mchk
2364 lda r25, mchk_c_bugcheck(r31)
2376 lda r25, scb_v_procmchk(r31) // Get SCB vector
2385 ldah r14, 0xfff0(r31)
2396 br r31, sys_mchk_collect_iprs // Join common machine check flow
2418 mfpr r31, pt0 // Pad exc_addr read
2419 mfpr r31, pt0
2429 lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt
2430 br r31, sys_enter_console // enter the console
2448 br r31, sys_cflush
2466 ldah r14, 0x100(r31) // Init counter. Value?
2482 br r31, call_pal_halt
2488 br r31, osfpal_calpal_opcdec
2492 br r31, osfpal_calpal_opcdec
2496 br r31, osfpal_calpal_opcdec
2500 br r31, osfpal_calpal_opcdec
2504 br r31, osfpal_calpal_opcdec
2508 br r31, osfpal_calpal_opcdec
2527 br r31, sys_cserve
2553 or r16, r31, r3 // set r3 incase this is a address
2572 lda r2, 0x3FFF(r31) // get pal base checker mask
2578 br r31, swppal_cont
2584 br r31, osfpal_calpal_opcdec
2588 br r31, osfpal_calpal_opcdec
2608 br r31, sys_wripir
2614 br r31, osfpal_calpal_opcdec
2618 br r31, osfpal_calpal_opcdec
2657 ornot r31, r13, r13 // Flip all the bits
2677 br r31, osfpal_calpal_opcdec
2681 br r31, osfpal_calpal_opcdec
2685 br r31, osfpal_calpal_opcdec
2689 br r31, osfpal_calpal_opcdec
2693 br r31, osfpal_calpal_opcdec
2697 br r31, osfpal_calpal_opcdec
2701 br r31, osfpal_calpal_opcdec
2705 br r31, osfpal_calpal_opcdec
2709 br r31, osfpal_calpal_opcdec
2713 br r31, osfpal_calpal_opcdec
2717 br r31, osfpal_calpal_opcdec
2721 br r31, osfpal_calpal_opcdec
2725 br r31, osfpal_calpal_opcdec
2729 br r31, osfpal_calpal_opcdec
2733 br r31, osfpal_calpal_opcdec
2737 br r31, osfpal_calpal_opcdec
2741 br r31, osfpal_calpal_opcdec
2745 br r31, osfpal_calpal_opcdec
2749 br r31, osfpal_calpal_opcdec
2753 br r31, osfpal_calpal_opcdec
2757 br r31, osfpal_calpal_opcdec
2761 br r31, osfpal_calpal_opcdec
2765 br r31, osfpal_calpal_opcdec
2769 br r31, osfpal_calpal_opcdec
2773 br r31, osfpal_calpal_opcdec
2792 or r31, 1, r13 // Get a one
2807 mfpr r31, pt0 // Pad ICSR<FPE> write.
2808 mfpr r31, pt0
2810 mfpr r31, pt0
2817 br r31, osfpal_calpal_opcdec
2839 br r31, osfpal_calpal_opcdec
2843 br r31, osfpal_calpal_opcdec
2881 ldah r24, (1<<(icsr_v_fpe-16))(r31)
2887 br r31, swpctx_cont
2948 jmp r31, (r23) // and go do it
2981 jmp r31, (r23) // and go do it
3005 bis r11, r31, r0 // return old ipl
3007 bis r16, r31, r11 // set new ps
3010 mfpr r31, pt0 // pad ipl write
3011 mfpr r31, pt0 // pad ipl write
3027 bis r11, r31, r0 // Fetch PALshadow PS
3168 br r31, perfmon_unknown // br if unknown request
3189 br r31, osfpal_calpal_opcdec
3225 bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr
3231 stl_c r31, -4(sp) // clear lock_flag
3233 lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user
3237 mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei
3245 rc r31 // clear inter_flag
3252 br r31, osfpal_calpal_opcdec
3274 bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
3277 rc r31 // clear intr_flag
3289 stl_c r31, -4(r25) // clear lock_flag
3295 br r31, rti_to_user // out of call_pal space
3322 mtpr r31, ev5__ps // Set Ibox current mode to kernel
3324 bis r11, r31, r12 // Save PS for stack write
3327 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
3331 bis r31, r31, r11 // Set new PS
3339 bis r31, osf_a0_bpt, r16 // set a0
3342 br r31, bpt_bchk_common // out of call_pal space
3363 mtpr r31, ev5__ps // Set Ibox current mode to kernel
3365 bis r11, r31, r12 // Save PS for stack write
3368 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
3372 bis r31, r31, r11 // Set new PS
3380 bis r31, osf_a0_bugchk, r16 // set a0
3383 br r31, bpt_bchk_common // out of call_pal space
3388 br r31, osfpal_calpal_opcdec
3416 mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
3417 mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
3419 bis r31, r31, r11 // PS=0 (mode=kern)
3439 br r31, osfpal_calpal_opcdec
3443 br r31, osfpal_calpal_opcdec
3459 mfpr r31, ev5__mcsr // Sync with clear
3462 br r31, pal_ic_flush // Flush Icache
3469 br r31, osfpal_calpal_opcdec
3473 br r31, osfpal_calpal_opcdec
3477 br r31, osfpal_calpal_opcdec
3481 br r31, osfpal_calpal_opcdec
3485 br r31, osfpal_calpal_opcdec
3489 br r31, osfpal_calpal_opcdec
3493 br r31, osfpal_calpal_opcdec
3497 br r31, osfpal_calpal_opcdec
3501 br r31, osfpal_calpal_opcdec
3505 br r31, osfpal_calpal_opcdec
3509 br r31, osfpal_calpal_opcdec
3513 br r31, osfpal_calpal_opcdec
3517 br r31, osfpal_calpal_opcdec
3521 br r31, osfpal_calpal_opcdec
3525 br r31, osfpal_calpal_opcdec
3529 br r31, osfpal_calpal_opcdec
3533 br r31, osfpal_calpal_opcdec
3537 br r31, osfpal_calpal_opcdec
3541 br r31, osfpal_calpal_opcdec
3545 br r31, osfpal_calpal_opcdec
3549 br r31, osfpal_calpal_opcdec
3553 br r31, osfpal_calpal_opcdec
3557 br r31, osfpal_calpal_opcdec
3600 br r31, osfpal_calpal_opcdec
3604 br r31, osfpal_calpal_opcdec
3608 br r31, osfpal_calpal_opcdec
3612 br r31, osfpal_calpal_opcdec
3616 br r31, osfpal_calpal_opcdec
3620 br r31, osfpal_calpal_opcdec
3624 br r31, osfpal_calpal_opcdec
3628 br r31, osfpal_calpal_opcdec
3632 br r31, osfpal_calpal_opcdec
3636 br r31, osfpal_calpal_opcdec
3659 mtpr r31, ev5__ps // Set Ibox current mode to kernel
3661 bis r11, r31, r12 // Save PS for stack write
3664 mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
3668 bis r31, r31, r11 // Set new PS
3676 bis r31, osf_a0_gentrap, r16// set a0
3679 br r31, bpt_bchk_common // out of call_pal space
3686 br r31, osfpal_calpal_opcdec
3690 br r31, osfpal_calpal_opcdec
3694 br r31, osfpal_calpal_opcdec
3698 br r31, osfpal_calpal_opcdec
3702 br r31, osfpal_calpal_opcdec
3706 br r31, osfpal_calpal_opcdec
3710 br r31, osfpal_calpal_opcdec
3714 br r31, osfpal_calpal_opcdec
3718 br r31, osfpal_calpal_opcdec
3722 br r31, osfpal_calpal_opcdec
3726 br r31, osfpal_calpal_opcdec
3730 br r31, osfpal_calpal_opcdec
3734 br r31, osfpal_calpal_opcdec
3738 br r31, osfpal_calpal_opcdec
3742 br r31, osfpal_calpal_opcdec
3746 br r31, osfpal_calpal_opcdec
3750 br r31, osfpal_calpal_opcdec
3754 br r31, osfpal_calpal_opcdec
3758 br r31, osfpal_calpal_opcdec
3762 br r31, osfpal_calpal_opcdec
3767 br r31, copypal_impl
3784 lda r8, 1(r31) // get a 1
3794 ldah r14, 0xfff0(r31)
3802 lda r8, 0x3F(r31) // build mux select mask
3818 br r31, perfmon_success
3826 lda r8, 3(r31)
3832 lda r8, 3(r31)
3838 lda r8, 3(r31)
3850 lda r17, 0x3F(r31) // build mask
3859 br r31, perfmon_success
3867 lda r9, 1(r31) // set enclr flag
3871 bis r31, r31, r9 // clear enclr flag
3887 lda r12, 1<<icsr_v_pmp(r31) // pb
3893 bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable)
3896 bis r14, r31, r13 // copy pmctr
3902 lda r8, 0xffff(r31)
3909 //orig get_addr r8, 3<<pmctr_v_ctl0, r31
3920 lda r8, 0xffff(r31)
3927 //orig get_addr r8, 3<<pmctr_v_ctl1, r31
3938 lda r8, 0x3FFF(r31) // ctr2<13:0> mask
3944 //orig get_addr r8, 3<<pmctr_v_ctl2, r31
3956 lda r8, 0x3F(r31)
3969 br r31, perfmon_success
3992 lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0
3994 cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1
3997 mfpr r31, pt0 // pad icsr write
3998 mfpr r31, pt0 // pad icsr write
4008 br r31, perfmon_success
4017 lda r8, 0x3F(r31)
4030 br r31, perfmon_success
4041 lda r8, 0x3FFF(r31) // ctr2<13:0> mask
4052 mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy)
4055 or r31, 1, r0 // set success
4059 or r31, r31, r0 // set fail
4115 br r31, finished
4122 br r31, finished
4129 subq r31, r10, r10
4177 br r31, finished
4185 lda r12, -1(r31)