Lines Matching refs:r13
112 // r13 local scratch
226 mfpr r13, pt_entmm // get entry point
234 mtpr r13, exc_addr // load exc_addr with entMM
259 mfpr r13, ev5__intid // Fetch level of interruptor
268 cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl
292 subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL
295 subq r13, 0x1d, r9 // Check for 1d, 1e, 1f
498 srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits
503 and r13, 0x1F, r8 // isolate ra
528 srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode
571 mfpr r13, ev5__mm_stat // Get mmstat
574 srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits
588 blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm
591 srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits
600 and r13, 0xf, r13 // Clean extra bits in mm_stat
673 mfpr r13, pt_entif // get entry point
682 mtpr r13, exc_addr // load exc_addr with entIF
731 mfpr r13, ev5__exc_sum // get the exc_sum
743 srl r13, exc_sum_v_swc, r16 // shift data to correct position
780 mfpr r13, ev5__icsr
795 srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0
799 mfpr r13, pt_entif // get entry point
813 mtpr r13, exc_addr // load exc_addr with entIF
827 mtpr r13, exc_addr // load exc_addr with entIF
846 // r13 - MMstat
856 and r13, 1, r18 // Clean r/w bit for a2
862 srl r13, 1, r17 // shift fault bits to right position
885 // r13 - shifted MMstat
895 and r13, mm_stat_m_ra, r18 // Clean Ra for a2
1128 mfpr r13, pt_entif // get entry point
1134 mtpr r13, exc_addr // load exc_addr with entIF
1204 subl r23, r13, r13 // gen new cc offset
1213 insll r13, 4, r13 // >> 32
1217 mtpr r13, cc // set new offset
1297 mfpr r13, pt_entmm // get entry point
1315 mtpr r13, exc_addr // set vector address
1356 mfpr r13, pt_entmm // get entry point
1374 mtpr r13, exc_addr // set vector address
1442 and r9, 1, r13 // save r/w flag
1454 cmovlbs r13, r25, r12 // if write access move acv based on write enable
1456 or r13, r31, r18 // pass flag of dstream access and read vs write
1460 mfpr r13, pt_entmm // get entry point
1463 mtpr r13, exc_addr // set vector address
1651 mfpr r13, pt_entif // get entry point
1660 mtpr r13, exc_addr // load exc_addr with entIF
1688 pal_update_pcb_20_: rpcc r13 // get cyccounter
1689 srl r13, 32, r14 // move offset
1690 addl r13, r14, r14 // merge for new time
1795 SAVE_GPR(r13,CNS_Q_GPR+0x68,r1)
1863 SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
1908 ldq_p r13, ldLock(r14)
1922 SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1);
2230 RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
2270 RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1)
2471 mfpr r13, ev5__maf_mode // Fetch status bit
2473 srl r13, maf_mode_v_dread_pending, r13
2477 blbs r13, DRAINA_LOOP // Wait until all DREADS clear
2654 and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE
2657 ornot r31, r13, r13 // Flip all the bits
2660 and r14, r13, r1 // Update MCHK, SCE, PCE
2792 or r31, 1, r13 // Get a one
2795 sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0
2799 bic r1, r13, r1 // zero icsr<fpe>
2864 rpcc r13 // get cyccounter
2870 srl r13, 32, r25 // move offset
2878 addl r13, r25, r25 // merge for new time
3280 ldq r13, -5*8(r25) // pc
3288 bic r13, 3, r13 // clean return pc
3292 mtpr r13, exc_addr // set return address
3883 mfpr r13, icsr
3888 bic r13, r12, r13 // clear pmp bit
3890 or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear
3891 mtpr r13, icsr // update icsr
3896 bis r14, r31, r13 // copy pmctr
3906 bic r13, r8, r13 // clear ctr bits
3924 bic r13, r8, r13 // clear ctr bits
3941 bic r13, r8, r13 // clear ctr bits
3951 cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr
3953 mtpr r13, ev5__pmctr // update pmctr ipr
4136 ldq_u r13, 0(r16)
4137 mskql r13, r16, r13
4138 bis r12, r13, r12
4153 extqh r9, r17, r13
4155 bis r12, r13, r13
4156 stq r13, 0(r16)
4162 extqh r8, r17, r13
4163 bis r12, r13, r13
4165 stq r13, 0(r16)
4186 mskql r12, r18, r13
4187 cmovne r13, r13, r12
4188 insqh r12, r16, r13
4194 bic r25, r13, r25
4196 and r9, r13, r9