alpha/palcode/osfpal.S

1185         bic	r25, r24, r25		// clean icsr<FPE,PMP>
1191         or	r25, r12, r25		// icsr with new fen
1200         or	r25, r22, r25		// icsr with new pme
1208         mtpr	r25, icsr		// write the icsr
1774         mfpr	r2, icsr		// Get icsr
1777         mtpr	r0, icsr		// Turn off SDE
1848         mfpr	r31, pt0		// pad write to icsr out of shadow of store (trap does not abort write)
1850         mtpr	r2, icsr		// Restore original ICSR
1871         SAVE_IPR(icsr,CNS_Q_ICSR,r1)
1936         mfpr	r0, icsr		// get icsr
1940         mtpr	r0, icsr		// write to icsr, enabling FEN
2088         mfpr	r0, icsr		// Get current ICSR
2093         mtpr	r0, icsr		// Update the chip
2239         mfpr	r31, pt0		// pad last load to icsr write (in case of replay, icsr will be written anyway)
2241         mfpr	r0, icsr		// Get icsr
2244         mtpr	r2, icsr		// Turn off SDE - no palshadow rd/wr for 3 bubble cycles
2293 //orig	restore_reg icsr, ipr=1		// restore original icsr- 4 bubbles to hw_rei
2297         RESTORE_IPR(icsr,CNS_Q_ICSR,r1)
2795         sll	r13, icsr_v_fpe, r13	// shift 1 to icsr<fpe> spot, e0
2799         bic	r1, r13, r1		// zero icsr<fpe>
2884         mfpr	r25, icsr		// get current icsr
3883         mfpr	r13, icsr
3889         sll	r16, icsr_v_pmp, r12	// move pme bit to icsr<pmp> position
3890         or	r12, r13, r13		// new icsr with icsr<pmp> bit set/clear
3891         mtpr	r13, icsr		// update icsr
3893         bis	r31, 1, r16		// set r16<0> on pass2 to update pmctr always (icsr provides real enable)
3991         mfpr	r8, icsr
3992         lda	r25, 1<<icsr_v_pma(r31)		// set icsr<pma> if r17<0>=0
3994         cmovlbs r17, r31, r25			// and clear icsr<pma> if r17<0>=1
3996         mtpr	r8, icsr		// 4 bubbles to hw_rei
3997         mfpr	r31, pt0			// pad icsr write
3998         mfpr	r31, pt0			// pad icsr write