Lines Matching defs:controller
107 // This is the hit latency unless the top-level cache controller
113 //! that exist with in the controller.
128 //! version 0 of this controller type.
211 //! Histogram for profiling delay for the messages this controller
217 //! controller of this type.
231 * memory controller. It has a queue of packets not yet sent.
241 AbstractController *controller;
248 // Currently the pkt is handed to the coherence controller
253 /* Master port to the memory controller. */
256 // State that is stored in packets sent to the memory controller.
267 /** The address range to which the controller responds on the CPU side. */