src/mem/dramsim2.cc

42 #include "DRAMSim2/Callback.h"
45 #include "debug/DRAMSim2.hh"
49 DRAMSim2::DRAMSim2(const Params* p) :
59     DPRINTF(DRAMSim2,
60             "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
64         new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
65             this, &DRAMSim2::readComplete);
67         new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
68             this, &DRAMSim2::writeComplete);
72     // being called. The callback prints the DRAMSim2 stats.
79 DRAMSim2::init()
84         fatal("DRAMSim2 %s is unconnected!\n", name());
90         fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
95 DRAMSim2::startup()
104 DRAMSim2::sendResponse()
109     DPRINTF(DRAMSim2, "Attempting to send response\n");
115         DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n",
127         DPRINTF(DRAMSim2, "Waiting for response retry\n");
134 DRAMSim2::nbrOutstanding() const
140 DRAMSim2::tick()
155 DRAMSim2::recvAtomic(PacketPtr pkt)
164 DRAMSim2::recvFunctional(PacketPtr pkt)
178 DRAMSim2::recvTimingReq(PacketPtr pkt)
226         DPRINTF(DRAMSim2, "Enqueueing address %lld\n", pkt->getAddr());
241 DRAMSim2::recvRespRetry()
243     DPRINTF(DRAMSim2, "Retrying\n");
251 DRAMSim2::accessAndRespond(PacketPtr pkt)
253     DPRINTF(DRAMSim2, "Access for address %lld\n", pkt->getAddr());
271         DPRINTF(DRAMSim2, "Queuing response for address %lld\n",
287 void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
292     DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
315 void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
320     DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
340 DRAMSim2::getPort(const std::string &if_name, PortID idx)
350 DRAMSim2::drain()
357 DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
358                                  DRAMSim2& _memory)
363 DRAMSim2::MemoryPort::getAddrRanges() const
371 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
377 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
383 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
390 DRAMSim2::MemoryPort::recvRespRetry()
395 DRAMSim2*
398     return new DRAMSim2(this);