src/mem/dram_ctrl.cc

1726       refreshState(REF_IDLE), inLowPowerState(false), rank(rank),
1797     if (refreshState == REF_DRAIN) {
1800         refreshState = REF_PD_EXIT;
1891     if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) {
1896         refreshState = REF_DRAIN;
1908     if (refreshState == REF_DRAIN) {
1919             refreshState = REF_PD_EXIT;
1924     if (refreshState == REF_PD_EXIT) {
1933             refreshState = REF_PRE;
1938     if (refreshState == REF_PRE) {
2000     if (refreshState == REF_START) {
2031         refreshState = REF_RUN;
2036     if (refreshState == REF_RUN) {
2171     if (refreshState == REF_PD_EXIT) {
2258         refreshState = REF_IDLE;
2276     if ((pwrState == PWR_ACT) && (refreshState == REF_PD_EXIT)) {
2281         refreshState = REF_PRE;
2290             refreshState = REF_SREF_EXIT;
2295             if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) {
2303                     if (refreshState == REF_PD_EXIT) {
2308                     } else if (refreshState == REF_PRE) {
2325         assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT);
2358             refreshState = REF_START;