mem/cache/base.hh

192          * @param pkt The packet to check for conflicts against.
194         bool checkConflictingSnoop(const PacketPtr pkt)
196             if (snoopRespQueue.checkConflict(pkt, cache.blkSize)) {
226         virtual void recvTimingSnoopReq(PacketPtr pkt);
228         virtual bool recvTimingResp(PacketPtr pkt);
230         virtual Tick recvAtomicSnoop(PacketPtr pkt);
232         virtual void recvFunctionalSnoop(PacketPtr pkt);
293         virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
295         virtual bool tryTiming(PacketPtr pkt) override;
297         virtual bool recvTimingReq(PacketPtr pkt) override;
299         virtual Tick recvAtomic(PacketPtr pkt) override;
301         virtual void recvFunctional(PacketPtr pkt) override;
452      * @param pkt The memory request to perform.
458     virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
468     virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
482     virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
497     void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
502      * @param pkt The request to perform.
504     virtual void recvTimingReq(PacketPtr pkt);
510     void handleUncacheableWriteResp(PacketPtr pkt);
519      * @param pkt The response packet
522     virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
527      * @param pkt The response packet
529     virtual void recvTimingResp(PacketPtr pkt);
533      * @param pkt The current bus transaction.
535     virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
539      * @param pkt Snoop response packet
541     virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
550      * @param pkt The packet with the requests
555     virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
560      * @param pkt The request to perform.
563     virtual Tick recvAtomic(PacketPtr pkt);
568      * @param pkt The memory request to snoop
571     virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
576      * @param pkt The request to perform.
579     virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
584     void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
692      * @param pkt Request packet from upstream that hit a block
697     virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
724      * @param pkt The memory request with the fill data.
730     CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
741      * @param pkt Packet holding the address to update
745     CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
1071     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
1073         MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
1074                                         pkt, time, order++,
1075                                         allocOnFill(pkt->cmd));
1089     void allocateWriteBuffer(PacketPtr pkt, Tick time)
1092         assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1094         Addr blk_addr = pkt->getBlockAddr(blkSize);
1101             time += pkt->payloadDelay;
1102             pkt->payloadDelay = 0;
1106             writeBuffer.findMatch(blk_addr, pkt->isSecure());
1108             DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1111         writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1194     void incMissCount(PacketPtr pkt)
1196         assert(pkt->req->masterId() < system->maxMasters());
1197         misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
1198         pkt->req->incAccessDepth();
1205     void incHitCount(PacketPtr pkt)
1207         assert(pkt->req->masterId() < system->maxMasters());
1208         hits[pkt->cmdToIndex()][pkt->req->masterId()]++;