Lines Matching defs:misses
903 /** The number of misses to trigger an exit event. */
929 /** Number of misses per thread for each type of command.
931 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
932 /** Number of misses for demand accesses. */
934 /** Number of misses for all accesses. */
942 /** Total number of cycles spent waiting for demand misses. */
944 /** Total number of cycles spent waiting for all misses. */
963 /** The average miss latency for demand misses. */
965 /** The average miss latency for all misses. */
982 /** Number of misses that hit in the MSHRs per command and thread. */
984 /** Demand misses that hit in the MSHRs. */
986 /** Total number of misses that hit in the MSHRs. */
989 /** Number of misses that miss in the MSHRs, per command and thread. */
991 /** Demand misses that miss in the MSHRs. */
993 /** Total number of misses that miss in the MSHRs. */
996 /** Number of misses that miss in the MSHRs, per command and thread. */
998 /** Total number of misses that miss in the MSHRs. */
1003 /** Total cycle latency of demand MSHR misses. */
1005 /** Total cycle latency of overall MSHR misses. */
1010 /** Total cycle latency of overall MSHR misses. */
1197 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;