Lines Matching refs:bridge
47 * Implementation of a memory-mapped bridge that connects a master
51 #include "mem/bridge.hh"
62 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
73 : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
105 fatal("Both ports of a bridge must be connected.\n");
135 // the two sides of the bridge are synchronous)
139 slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) +
188 // payload (unless the two sides of the bridge are
193 masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) +
223 bridge.schedule(sendEvent, when);
240 bridge.schedule(sendEvent, when);
269 bridge.schedule(sendEvent, std::max(next_req.tick,
270 bridge.clockEdge()));
310 bridge.schedule(sendEvent, std::max(next_resp.tick,
311 bridge.clockEdge()));
346 return delay * bridge.clockPeriod() + masterPort.sendAtomic(pkt);