learning_gem5/part2/simple_cache.cc

72 SimpleCache::CPUSidePort::sendPacket(PacketPtr pkt)
79     DPRINTF(SimpleCache, "Sending %s to CPU\n", pkt->print());
80     if (!sendTimingResp(pkt)) {
82         blockedPacket = pkt;
104 SimpleCache::CPUSidePort::recvFunctional(PacketPtr pkt)
107     return owner->handleFunctional(pkt);
111 SimpleCache::CPUSidePort::recvTimingReq(PacketPtr pkt)
113     DPRINTF(SimpleCache, "Got request %s\n", pkt->print());
122     if (!owner->handleRequest(pkt, id)) {
140     PacketPtr pkt = blockedPacket;
143     DPRINTF(SimpleCache, "Retrying response pkt %s\n", pkt->print());
145     sendPacket(pkt);
152 SimpleCache::MemSidePort::sendPacket(PacketPtr pkt)
159     if (!sendTimingReq(pkt)) {
160         blockedPacket = pkt;
165 SimpleCache::MemSidePort::recvTimingResp(PacketPtr pkt)
168     return owner->handleResponse(pkt);
178     PacketPtr pkt = blockedPacket;
182     sendPacket(pkt);
192 SimpleCache::handleRequest(PacketPtr pkt, int port_id)
199     DPRINTF(SimpleCache, "Got request for addr %#x\n", pkt->getAddr());
209     schedule(new EventFunctionWrapper([this, pkt]{ accessTiming(pkt); },
217 SimpleCache::handleResponse(PacketPtr pkt)
220     DPRINTF(SimpleCache, "Got response for addr %#x\n", pkt->getAddr());
224     insert(pkt);
237         delete pkt; // We may need to delay this, I'm not sure.
238         pkt = originalPacket;
240     } // else, pkt contains the data it needs
242     sendResponse(pkt);
247 void SimpleCache::sendResponse(PacketPtr pkt)
250     DPRINTF(SimpleCache, "Sending resp for addr %#x\n", pkt->getAddr());
262     cpuPorts[port].sendPacket(pkt);
272 SimpleCache::handleFunctional(PacketPtr pkt)
274     if (accessFunctional(pkt)) {
275         pkt->makeResponse();
277         memPort.sendFunctional(pkt);
282 SimpleCache::accessTiming(PacketPtr pkt)
284     bool hit = accessFunctional(pkt);
287             pkt->print());
292         DDUMP(SimpleCache, pkt->getConstPtr<uint8_t>(), pkt->getSize());
293         pkt->makeResponse();
294         sendResponse(pkt);
301         Addr addr = pkt->getAddr();
302         Addr block_addr = pkt->getBlockAddr(blockSize);
303         unsigned size = pkt->getSize();
307             memPort.sendPacket(pkt);
313             assert(pkt->needsResponse());
315             if (pkt->isWrite() || pkt->isRead()) {
324             PacketPtr new_pkt = new Packet(pkt->req, cmd, blockSize);
331             originalPacket = pkt;
340 SimpleCache::accessFunctional(PacketPtr pkt)
342     Addr block_addr = pkt->getBlockAddr(blockSize);
345         if (pkt->isWrite()) {
347             pkt->writeDataToBlock(it->second, blockSize);
348         } else if (pkt->isRead()) {
350             pkt->setDataFromBlock(it->second, blockSize);
360 SimpleCache::insert(PacketPtr pkt)
363     assert(pkt->getAddr() ==  pkt->getBlockAddr(blockSize));
365     assert(cacheStore.find(pkt->getAddr()) == cacheStore.end());
366     // The pkt should be a response
367     assert(pkt->isResponse());
389         DPRINTF(SimpleCache, "Writing packet back %s\n", pkt->print());
397     DPRINTF(SimpleCache, "Inserting %s\n", pkt->print());
398     DDUMP(SimpleCache, pkt->getConstPtr<uint8_t>(), blockSize);
404     cacheStore[pkt->getAddr()] = data;
407     pkt->writeDataToBlock(data, blockSize);