Lines Matching defs:tc

277     GpuTLB::translateInt(const RequestPtr &req, ThreadContext *tc)
624 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
653 ThreadContext *tc, bool update_stats)
664 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
701 GpuTLB::translate(const RequestPtr &req, ThreadContext *tc,
712 return translateInt(req, tc);
719 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
732 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) {
737 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
751 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
752 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
757 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
796 "at pc %#x.\n", vaddr, tc->instAddr());
798 Process *p = tc->getProcessPtr();
840 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
887 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
895 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
904 GpuTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc,
909 return GpuTLB::translate(req, tc, nullptr, mode, delayedResponse, false,
914 GpuTLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
920 Fault fault = GpuTLB::translate(req, tc, translation, mode,
924 translation->finish(fault, req, tc, mode);
1045 ThreadContext * tmp_tc = sender_state->tc;
1071 auto p = sender_state->tc->getProcessPtr();
1125 GpuTLB::pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt,
1128 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
1134 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
1169 ThreadContext *tc = sender_state->tc;
1207 pagingProtectionChecks(tc, pkt, local_entry, mode);
1322 Process *p = sender_state->tc->getProcessPtr();
1415 ThreadContext *tc = sender_state->tc;
1465 pagingProtectionChecks(tc, pkt, local_entry, mode);
1485 ThreadContext *tc = sender_state->tc;
1495 bool success = tlb->tlbLookup(pkt->req, tc, update_stats);
1523 Process *p = tc->getProcessPtr();
1580 auto p = sender_state->tc->getProcessPtr();