Lines Matching refs:unitId
66 ExecStage::collectStatistics(enum STAT_STATUS stage, int unitId) {
70 if (computeUnit->isVecAlu(unitId) && vectorAluInstAvail->at(unitId)) {
71 numCyclesWithNoInstrTypeIssued[unitId]++;
76 if (computeUnit->isGlbMem(unitId) && *glbMemInstAvail > 0) {
77 numCyclesWithNoInstrTypeIssued[unitId]++;
83 if (computeUnit->isShrMem(unitId) && *shrMemInstAvail > 0) {
84 numCyclesWithNoInstrTypeIssued[unitId]++;
90 numCyclesWithInstrTypeIssued[unitId]++;
133 for (int unitId = 0; unitId < (numSIMDs + numMemUnits); ++unitId) {
136 if (dispatchList->at(unitId).second == EMPTY) {
137 collectStatistics(IdleExec, unitId);
141 collectStatistics(BusyExec, unitId);
143 dispatchList->at(unitId).first->exec();
145 dispatchList->at(unitId).second = EMPTY;
146 dispatchList->at(unitId).first = (Wavefront*)nullptr;