src/gpu-compute/compute_unit.cc

621 ComputeUnit::DataPort::recvTimingResp(PacketPtr pkt)
626     SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState);
631     if (pkt->req->isKernel() && pkt->req->isRelease()) {
657         delete pkt->senderState;
658         delete pkt;
660     } else if (pkt->req->isKernel() && pkt->req->isAcquire()) {
667         delete pkt->senderState;
668         delete pkt;
673         computeUnit->memPort[index]->createMemRespEvent(pkt);
677             index, pkt->req->getPaddr());
692         PacketPtr pkt = retries.front().first;
696                 pkt->req->getPaddr());
701         if (!sendTimingReq(pkt)) {
712 ComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt)
714     computeUnit->fetchStage.processFetchReturn(pkt);
727         PacketPtr pkt = retries.front().first;
731                 pkt->req->getPaddr());
732         if (!sendTimingReq(pkt)) {
743 ComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)
746     Addr tmp_vaddr = pkt->req->getVaddr();
751     pkt->req->setPC(gpuDynInst->wavefront()->pc());
753     pkt->req->setReqInstSeqNum(gpuDynInst->seqNum());
757     assert(pkt->isRead() || pkt->isWrite());
761     if (pkt->isWrite()){
763     } else if (pkt->isRead()) {
766         fatal("pkt is not a read nor a write\n");
777             Addr vaddr = pkt->req->getVaddr();
778             unsigned size = pkt->getSize();
797         pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index);
802                                                pkt->senderState);
804         pkt->senderState = translation_state;
807             tlbPort[tlbPort_index]->sendFunctional(pkt);
816                 safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
822             assert(pkt->req->hasPaddr());
823             assert(pkt->req->hasSize());
825             uint8_t *tmpData = pkt->getPtr<uint8_t>();
832             PacketPtr oldPkt = pkt;
833             pkt = new Packet(oldPkt->req, oldPkt->cmd);
835             pkt->dataStatic(tmpData);
839             pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst,
842             gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index);
849                 memPort[index]->createMemReqEvent(pkt);
853                     gpuDynInst->wfSlotId, index, pkt->req->getPaddr());
863             tlbPort[tlbPort_index]->retries.push_back(pkt);
864         } else if (!tlbPort[tlbPort_index]->sendTimingReq(pkt)) {
875             tlbPort[tlbPort_index]->retries.push_back(pkt);
882         if (pkt->cmd == MemCmd::MemFenceReq) {
889         delete pkt->senderState;
892         pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode,
895         tlbPort[tlbPort_index]->sendFunctional(pkt);
901         PacketPtr new_pkt = new Packet(pkt->req, pkt->cmd);
902         new_pkt->dataStatic(pkt->getPtr<uint8_t>());
913              safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
917         delete pkt->senderState;
918         delete pkt;
923 ComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)
926         memPort[index]->createMemReqEvent(pkt);
930     pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, index,
935             pkt->req->getPaddr());
965     PacketPtr pkt = new Packet(req, MemCmd::MemFenceReq);
968     pkt->senderState =
972     sendSyncRequest(gpuDynInst, 0, pkt);
976 ComputeUnit::DataPort::processMemRespEvent(PacketPtr pkt)
979         safe_cast<DataPort::SenderState*>(pkt->senderState);
988             pkt->req->getPaddr(), index);
990     Addr paddr = pkt->req->getPaddr();
992     if (pkt->cmd != MemCmd::MemFenceResp) {
996                 pkt->req->getPaddr(), index);
999         gpuDynInst->pAddr = pkt->req->getPaddr();
1001         if (pkt->isRead() || pkt->isWrite()) {
1058     delete pkt->senderState;
1059     delete pkt;
1069 ComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt)
1071     Addr line = pkt->req->getPaddr();
1074             pkt->req->getVaddr(), line);
1076     assert(pkt->senderState);
1081                safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1093                  pkt->req->getVaddr());
1102     pkt->senderState = translation_state->saved;
1104     // for prefetch pkt
1111         safe_cast<DTLBPort::SenderState*>(pkt->senderState);
1115     Addr vaddr = pkt->req->getVaddr();
1121     if (pkt->cmd == MemCmd::ReadResp) {
1123     } else if (pkt->cmd == MemCmd::WriteResp) {
1125     } else if (pkt->cmd == MemCmd::SwapResp) {
1129               pkt->cmd.toString());
1212     PacketPtr new_pkt = new Packet(pkt->req, requestCmd);
1213     new_pkt->dataStatic(pkt->getPtr<uint8_t>());
1214     delete pkt->senderState;
1215     delete pkt;
1238 ComputeUnit::DataPort::createMemReqEvent(PacketPtr pkt)
1241         [this, pkt]{ processMemReqEvent(pkt); },
1246 ComputeUnit::DataPort::createMemRespEvent(PacketPtr pkt)
1249         [this, pkt]{ processMemRespEvent(pkt); },
1254 ComputeUnit::DataPort::processMemReqEvent(PacketPtr pkt)
1256     SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState);
1260     if (!(sendTimingReq(pkt))) {
1261         retries.push_back(std::make_pair(pkt, gpuDynInst));
1267                 pkt->req->getPaddr());
1273                 pkt->req->getPaddr());
1298         PacketPtr pkt = retries.front();
1299         Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1302         if (!sendTimingReq(pkt)) {
1315 ComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt)
1317     Addr line M5_VAR_USED = pkt->req->getPaddr();
1319             computeUnit->cu_id, pkt->req->getVaddr(), line);
1321     assert(pkt->senderState);
1325                  safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1330     pkt->senderState = translation_state->saved;
1335         safe_cast<ITLBPort::SenderState*>(pkt->senderState);
1339     delete pkt->senderState;
1342         // pkt is reused in fetch(), don't delete it here.  However, we must
1345         assert(pkt->cmd == MemCmd::ReadResp);
1346         pkt->cmd = MemCmd::ReadReq;
1348         computeUnit->fetchStage.fetch(pkt, wavefront);
1382         PacketPtr pkt = retries.front();
1383         Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1386         if (!sendTimingReq(pkt)) {
1839 ComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt)
1842             dynamic_cast<ComputeUnit::LDSPort::SenderState*>(pkt->senderState);
1850         retries.push(pkt);
1856     } else if (!MasterPort::sendTimingReq(pkt)) {
1860         retries.push(pkt);
1864                 gpuDynInst->wfSlotId, pkt->req->getPaddr());
1869                 gpuDynInst->wfSlotId, pkt->req->getPaddr());