dev/storage/ide_disk.cc

100             panic("Bad IDE image size: 0\n");
178         panic("Invalid device ID: %#x\n", id);
205         panic("Access to unset controller!\n");
223             panic("Data read of unsupported size %d.\n", size);
253         panic("Invalid IDE command register offset: %#x\n", offset);
264         panic("Invalid IDE control register offset: %#x\n", offset);
279             panic("Data write of unsupported size %d.\n", size);
310         panic("Invalid IDE command register offset: %#x\n", offset);
320         panic("Invalid IDE control register offset: %#x\n", offset);
350         panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
581         panic("Can't read from %s. Only %d of %d read. errno=%d\n",
591         panic("Can't write to %s. Only %d of %d written. errno=%d\n",
603         panic("Inconsistent DMA state, should be in Dma_Start!\n");
606         panic("Inconsistent device state for DMA start!\n");
621         panic("Inconsistent DMA state, should be Start or Transfer!");
624         panic("Inconsistent device state, should be Transfer or Prepare!\n");
674             panic("Attempt to perform CHS access, only supports LBA\n");
692             panic("Attempt to perform CHS access, only supports LBA\n");
711             panic("Attempt to perform CHS access, only supports LBA\n");
726         panic("Unsupported ATA command: %#x\n", cmdReg.command);
750         panic("Attempt to post an interrupt with one pending\n");
765         panic("Attempt to clear a non-pending interrupt\n");
899                 panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
975                 panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
1026                 panic("Inconsistent DMA state, should be Dma_Idle\n");
1074         panic("Unknown IDE device state: %#x\n", devState);