Lines Matching refs:Regs

170     using namespace Regs;
225 Addr index = daddr >> Regs::VirtualShift;
226 Addr raddr = daddr & Regs::VirtualMask;
232 const Regs::Info &info = regInfo(raddr);
263 if (raddr == Regs::IntrStatus)
278 const Regs::Info &info = regInfo(daddr);
310 Addr index = daddr >> Regs::VirtualShift;
311 Addr raddr = daddr & Regs::VirtualMask;
317 const Regs::Info &info = regInfo(raddr);
339 case Regs::Config:
343 case Regs::Command:
347 case Regs::IntrStatus:
352 case Regs::IntrMask:
356 case Regs::RxData:
357 if (Regs::get_RxDone_Busy(vnic.RxDone))
362 vnic.RxDone = Regs::RxDone_Busy;
366 if (Regs::get_RxData_Vaddr(pkt->getLE<uint64_t>())) {
369 Addr vaddr = Regs::get_RxData_Addr(reg64);
375 vnic.RxData = Regs::set_RxData_Addr(vnic.RxData, paddr);
396 case Regs::TxData:
397 if (Regs::get_TxDone_Busy(vnic.TxDone))
402 vnic.TxDone = Regs::TxDone_Busy;
404 if (Regs::get_TxData_Vaddr(pkt->getLE<uint64_t>())) {
407 Addr vaddr = Regs::get_TxData_Addr(reg64);
413 vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr);
435 if ((interrupts & Regs::Intr_Res))
451 interrupts &= ~Regs::Intr_RxHigh;
458 interrupts &= ~Regs::Intr_TxLow;
462 if ((interrupts & Regs::Intr_NoDelay) == 0)
471 if ((interrupts & Regs::Intr_Res))
599 if ((changed & Regs::Config_IntEn)) {
600 cpuIntrEnable = regs.Config & Regs::Config_IntEn;
609 if ((changed & Regs::Config_TxEn)) {
610 txEnable = regs.Config & Regs::Config_TxEn;
615 if ((changed & Regs::Config_RxEn)) {
616 rxEnable = regs.Config & Regs::Config_RxEn;
625 if (command & Regs::Command_Intr)
626 devIntrPost(Regs::Intr_Soft);
628 if (command & Regs::Command_Reset)
635 using namespace Regs;
757 bool busy = Regs::get_RxDone_Busy(vn->RxDone);
841 vnic->rxDoneData |= Regs::RxDone_IpPacket;
845 vnic->rxDoneData |= Regs::RxDone_IpError;
854 vnic->rxDoneData |= Regs::RxDone_TcpPacket;
858 vnic->rxDoneData |= Regs::RxDone_TcpError;
861 vnic->rxDoneData |= Regs::RxDone_UdpPacket;
865 vnic->rxDoneData |= Regs::RxDone_UdpError;
877 rxDmaAddr = pciToDma(Regs::get_RxData_Addr(vnic->RxData));
878 rxDmaLen = min<unsigned>(Regs::get_RxData_Len(vnic->RxData),
885 if ((Regs::get_Config_ZeroCopy(regs.Config) ||
886 Regs::get_Config_DelayCopy(regs.Config)) &&
887 !Regs::get_RxData_NoDelay(vnic->RxData) && rxLow) {
907 vnic->RxDone |= Regs::RxDone_Complete;
915 vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone, rxDmaLen);
929 vnic->RxDone |= Regs::RxDone_More;
930 vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone,
942 devIntrPost(Regs::Intr_RxEmpty);
952 devIntrPost(Regs::Intr_RxDMA);
1028 interrupts = Regs::Intr_TxPacket;
1030 interrupts |= Regs::Intr_TxLow;
1056 assert(Regs::get_TxDone_Busy(vnic->TxDone));
1064 Regs::get_TxData_Len(vnic->TxData)) {
1076 txDmaAddr = pciToDma(Regs::get_TxData_Addr(vnic->TxData));
1077 txDmaLen = Regs::get_TxData_Len(vnic->TxData);
1089 vnic->TxDone = txDmaLen | Regs::TxDone_Complete;
1092 if ((vnic->TxData & Regs::TxData_More)) {
1095 devIntrPost(Regs::Intr_TxDMA);
1100 if ((vnic->TxData & Regs::TxData_Checksum)) {
1125 devIntrPost(Regs::Intr_TxFull);
1132 devIntrPost(Regs::Intr_TxDMA);
1168 if (!Regs::get_Config_Filter(regs.Config))
1196 devIntrPost(Regs::Intr_RxHigh);
1209 devIntrPost(Regs::Intr_RxPacket);