dev/arm/ufs_device.cc

896     UFSHCIMem.HCCAP = 0x06070000 | (UFSSlots & 0x1F);
897     UFSHCIMem.HCversion = 0x00010000; //version is 1.0
898     UFSHCIMem.HCHCDDID = 0xAA003C3C;// Arbitrary number
899     UFSHCIMem.HCHCPMID = 0x41524D48; //ARMH (not an official MIPI number)
900     UFSHCIMem.TRUTRLDBR = 0x00;
901     UFSHCIMem.TMUTMRLDBR = 0x00;
902     UFSHCIMem.CMDUICCMDR = 0x00;
904     UFSHCIMem.ORHostControllerStatus = 0x08;
905     UFSHCIMem.TRUTRLBA = 0x00;
906     UFSHCIMem.TRUTRLBAU = 0x00;
907     UFSHCIMem.TMUTMRLBA = 0x00;
908     UFSHCIMem.TMUTMRLBAU = 0x00;
937         data = UFSHCIMem.HCCAP;
941         data = UFSHCIMem.HCversion;
945         data = UFSHCIMem.HCHCDDID;
949         data = UFSHCIMem.HCHCPMID;
953         data = UFSHCIMem.ORInterruptStatus;
954         UFSHCIMem.ORInterruptStatus = 0x00;
960         data = UFSHCIMem.ORInterruptEnable;
964         data = UFSHCIMem.ORHostControllerStatus;
968         data = UFSHCIMem.ORHostControllerEnable;
972         data = UFSHCIMem.ORUECPA;
976         data = UFSHCIMem.ORUECDL;
980         data = UFSHCIMem.ORUECN;
984         data = UFSHCIMem.ORUECT;
988         data = UFSHCIMem.ORUECDME;
992         data = UFSHCIMem.ORUTRIACR;
996         data = UFSHCIMem.TRUTRLBA;
1000         data = UFSHCIMem.TRUTRLBAU;
1004         data = UFSHCIMem.TRUTRLDBR;
1008         data = UFSHCIMem.TRUTRLCLR;
1012         data = UFSHCIMem.TRUTRLRSR;
1016         data = UFSHCIMem.TMUTMRLBA;
1020         data = UFSHCIMem.TMUTMRLBAU;
1024         data = UFSHCIMem.TMUTMRLDBR;
1028         data = UFSHCIMem.TMUTMRLCLR;
1032         data = UFSHCIMem.TMUTMRLRSR;
1036         data = UFSHCIMem.CMDUICCMDR;
1040         data = UFSHCIMem.CMDUCMDARG1;
1044         data = UFSHCIMem.CMDUCMDARG2;
1048         data = UFSHCIMem.CMDUCMDARG3;
1108         UFSHCIMem.ORInterruptEnable = data;
1112         UFSHCIMem.ORHostControllerStatus = data;
1116         UFSHCIMem.ORHostControllerEnable = data;
1120         UFSHCIMem.ORUECPA = data;
1124         UFSHCIMem.ORUECDL = data;
1128         UFSHCIMem.ORUECN = data;
1132         UFSHCIMem.ORUECT = data;
1136         UFSHCIMem.ORUECDME = data;
1140         UFSHCIMem.ORUTRIACR = data;
1144         UFSHCIMem.TRUTRLBA = data;
1145         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1146             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU)!= 0x00))
1147             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1151         UFSHCIMem.TRUTRLBAU = data;
1152         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1153             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1154             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1158         if (!(UFSHCIMem.TRUTRLDBR) && data)
1160         UFSHCIMem.TRUTRLDBR |= data;
1165         UFSHCIMem.TRUTRLCLR = data;
1169         UFSHCIMem.TRUTRLRSR = data;
1173         UFSHCIMem.TMUTMRLBA = data;
1174         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1175             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1176             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1180         UFSHCIMem.TMUTMRLBAU = data;
1181         if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
1182             ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
1183             UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
1187         UFSHCIMem.TMUTMRLDBR |= data;
1192         UFSHCIMem.TMUTMRLCLR = data;
1196         UFSHCIMem.TMUTMRLRSR = data;
1200         UFSHCIMem.CMDUICCMDR = data;
1205         UFSHCIMem.CMDUCMDARG1 = data;
1209         UFSHCIMem.CMDUCMDARG2 = data;
1213         UFSHCIMem.CMDUCMDARG3 = data;
1246     while (((UFSHCIMem.CMDUICCMDR > 0x00) |
1247             ((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack) > 0x00) |
1248             ((UFSHCIMem.TRUTRLDBR ^ transferTrack) > 0x00)) ) {
1250         if (UFSHCIMem.CMDUICCMDR > 0x00) {
1256             UFSHCIMem.ORInterruptStatus |= UICCommandCOMPL;
1258             UFSHCIMem.CMDUICCMDR = 0x00;
1261         } else if ((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack) > 0x00) {
1268             count = findLsbSet((UFSHCIMem.TMUTMRLDBR ^ taskCommandTrack));
1269             address = UFSHCIMem.TMUTMRLBAU;
1272                 UFSHCIMem.TMUTMRLBA;
1281             task_info.done = UFSHCIMem.TMUTMRLDBR;
1289         } else if ((UFSHCIMem.TRUTRLDBR ^ transferTrack) > 0x00) {
1297             count = findLsbSet((UFSHCIMem.TRUTRLDBR ^ transferTrack));
1298             address = UFSHCIMem.TRUTRLBAU;
1300             address = (count * size) + (address << 32) + UFSHCIMem.TRUTRLBA;
1304                     " 0x%8x completion info: 0x%8x\n", UFSHCIMem.TRUTRLDBR,
1307             transferstart_info.done = UFSHCIMem.TRUTRLDBR;
1324             transferstart_info.done = UFSHCIMem.TRUTRLDBR;
1386     if (UFSHCIMem.CMDUICCMDR == 0x16) {
1387         UFSHCIMem.ORHostControllerStatus |= 0x0F;//link startup
1413     UFSHCIMem.TMUTMRLDBR &= ~(req_pos);
1415     UFSHCIMem.ORInterruptStatus |= UTPTaskREQCOMPL;
1527               UFSHCIMem.TRUTRLDBR);
1714               UFSHCIMem.TRUTRLDBR);
1754     if (UFSHCIMem.TRUTRLDBR & transferEnd.front().mask) {
1803     if (!(UFSHCIMem.ORInterruptStatus & 0x01)) {
1804         UFSHCIMem.ORInterruptStatus |= UTPTransferREQCOMPL;
1825     UFSHCIMem.TRUTRLDBR &= transferTrack;
1827     DPRINTF(UFSHostDevice, "Clear doorbell %X\n", UFSHCIMem.TRUTRLDBR);
1849     if (!(UFSHCIMem.TRUTRLDBR)) {
2302     const uint8_t* temp_HCI_mem = reinterpret_cast<const uint8_t*>(&UFSHCIMem);
2318     uint8_t* temp_HCI_mem = reinterpret_cast<uint8_t*>(&UFSHCIMem);
2334     if (UFSHCIMem.TRUTRLDBR) {
2353     if (UFSHCIMem.TRUTRLDBR) {