dev/arm/gic_v3_cpu_interface.cc

178           ICH_VMCR_EL2 ich_vmcr_el2 =
180           value = ich_vmcr_el2.VENG0;
196           ICH_VMCR_EL2 ich_vmcr_el2 =
198           value = ich_vmcr_el2.VENG1;
332         ICH_VMCR_EL2 ich_vmcr_el2 =
335         value = ich_vmcr_el2.VBPR0;
341         ICH_VMCR_EL2 ich_vmcr_el2 =
344         if (ich_vmcr_el2.VCBPR) {
346             value = ich_vmcr_el2.VBPR0 + 1;
349             value = ich_vmcr_el2.VBPR1;
381           ICH_VMCR_EL2 ich_vmcr_el2 =
384           value = ich_vmcr_el2.VPMR;
1098           ICH_VMCR_EL2 ich_vmcr_el2 =
1101           if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1117               ich_vmcr_el2.VBPR0 = val;
1119               ich_vmcr_el2.VBPR1 = val;
1122           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1218          ICH_VMCR_EL2 ich_vmcr_el2 =
1220          ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1221          ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1222          isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1314           ICH_VMCR_EL2 ich_vmcr_el2 =
1316           ich_vmcr_el2.VPMR = val & 0xff;
1318           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1338           ICH_VMCR_EL2 ich_vmcr_el2 =
1340           ich_vmcr_el2.VENG0 = enable;
1341           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1361           ICH_VMCR_EL2 ich_vmcr_el2 =
1363           ich_vmcr_el2.VENG1 = enable;
1364           isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1543           ICH_VMCR_EL2 ich_vmcr_el2 =
1545           ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1549               ich_vmcr_el2.VBPR0 = min_vpr0;
1551               ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1557               ich_vmcr_el2.VBPR1 = min_vpr1;
1559               ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1562           ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1563           ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1564           ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1565           ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1566           val = ich_vmcr_el2;
1951     ICH_VMCR_EL2 ich_vmcr_el2 =
1954     if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1961         bpr = ich_vmcr_el2.VBPR0;
1963         bpr = ich_vmcr_el2.VBPR1;
1994     ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1995     return ich_vmcr_el2.VEOIM;
2110     ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2112     if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2129             if (!ich_vmcr_el2.VENG1) {
2134             if (!ich_vmcr_el2.VENG0) {
2453     ICH_VMCR_EL2 ich_vmcr_el2 =
2506     if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2513     if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2520     if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2527     if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {