Lines Matching refs:warn
266 warn("Checkpoint does not contain CPU count, assuming %i CPUs\n",
356 warn("Ignoring write to read only count register: %s\n",
414 warn("Writing to unknown register: %s\n", miscRegName[reg]);
504 warn("Reading from unknown register: %s\n", miscRegName[reg]);
633 warn("Reading from unimplemented control register (0x%x)\n", addr);
643 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
652 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
669 warn("Write to unimplemented control register (0x%x)\n", addr);
683 warn("Ignoring write to unexpected address (0x%x:%i)\n",
694 warn("Ignoring write to unexpected address (0x%x:%i)\n",
724 warn("Read from unimplemented timer register (0x%x)\n", addr);
758 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
779 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
793 warn("Unimplemented timer register (0x%x)\n", addr);
833 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);
845 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);