Lines Matching defs:size

239     paramOut(cp, "cpu_count", timers.size());
243 for (int i = 0; i < timers.size(); ++i) {
286 if (cpu_id >= timers.size())
295 assert(timers.size() < cpus);
298 const unsigned old_cpu_count(timers.size());
570 const unsigned size(pkt->getSize());
576 value = ctrlRead(addr - ctrlRange.start(), size);
578 value = timerRead(addr - timerRange.start(), size);
583 DPRINTF(Timer, "Read 0x%x <- 0x%x(%i)\n", value, addr, size);
585 if (size == 8) {
587 } else if (size == 4) {
590 panic("Unexpected access size: %i\n", size);
599 const unsigned size(pkt->getSize());
600 if (size != 8 && size != 4)
601 panic("Unexpected access size\n");
604 const uint64_t value(size == 8 ?
607 DPRINTF(Timer, "Write 0x%x -> 0x%x(%i)\n", value, addr, size);
609 ctrlWrite(addr - ctrlRange.start(), size, value);
611 timerWrite(addr - timerRange.start(), size, value);
621 GenericTimerMem::ctrlRead(Addr addr, size_t size) const
623 if (size == 4) {
643 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
646 } else if (size == 8) {
652 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
656 panic("Invalid access size: %i\n", size);
661 GenericTimerMem::ctrlWrite(Addr addr, size_t size, uint64_t value)
663 if (size == 4) {
684 addr, size);
687 } else if (size == 8) {
695 addr, size);
699 panic("Invalid access size: %i\n", size);
704 GenericTimerMem::timerRead(Addr addr, size_t size) const
706 if (size == 4) {
758 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
761 } else if (size == 8) {
779 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size);
783 panic("Invalid access size: %i\n", size);
788 GenericTimerMem::timerWrite(Addr addr, size_t size, uint64_t value)
790 if (size == 4) {
833 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);
836 } else if (size == 8) {
845 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size);
849 panic("Invalid access size: %i\n", size);