src/cpu/simple_thread.hh

290         DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
301         DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
307     readVecReg(const RegId& reg) const override
309         int flatIndex = isa->flattenVecIndex(reg.index());
312         DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
313                 reg.index(), flatIndex, regVal.print());
318     getWritableVecReg(const RegId& reg) override
320         int flatIndex = isa->flattenVecIndex(reg.index());
323         DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
324                 reg.index(), flatIndex, regVal.print());
333     readVecLane(const RegId& reg) const
335         int flatIndex = isa->flattenVecIndex(reg.index());
337         auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
339                 reg.index(), flatIndex, reg.elemIndex(), regVal);
345     readVec8BitLaneReg(const RegId &reg) const override
347         return readVecLane<uint8_t>(reg);
352     readVec16BitLaneReg(const RegId &reg) const override
354         return readVecLane<uint16_t>(reg);
359     readVec32BitLaneReg(const RegId &reg) const override
361         return readVecLane<uint32_t>(reg);
366     readVec64BitLaneReg(const RegId &reg) const override
368         return readVecLane<uint64_t>(reg);
374     setVecLaneT(const RegId &reg, const LD &val)
376         int flatIndex = isa->flattenVecIndex(reg.index());
378         setVecLaneFlat(flatIndex, reg.elemIndex(), val);
380                 reg.index(), flatIndex, reg.elemIndex(), val);
383     setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
385         return setVecLaneT(reg, val);
388     setVecLane(const RegId &reg,
391         return setVecLaneT(reg, val);
394     setVecLane(const RegId &reg,
397         return setVecLaneT(reg, val);
400     setVecLane(const RegId &reg,
403         return setVecLaneT(reg, val);
408     readVecElem(const RegId &reg) const override
410         int flatIndex = isa->flattenVecElemIndex(reg.index());
412         const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
413         DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
414                 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
419     readVecPredReg(const RegId &reg) const override
421         int flatIndex = isa->flattenVecPredIndex(reg.index());
424         DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
425                 reg.index(), flatIndex, regVal.print());
430     getWritableVecPredReg(const RegId &reg) override
432         int flatIndex = isa->flattenVecPredIndex(reg.index());
436                 "Reading predicate reg %d (%d) as %s for modify.\n",
437                 reg.index(), flatIndex, regVal.print());
449         DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
463         DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
477         DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
482     setVecReg(const RegId &reg, const VecRegContainer &val) override
484         int flatIndex = isa->flattenVecIndex(reg.index());
487         DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
488                 reg.index(), flatIndex, val.print());
492     setVecElem(const RegId &reg, const VecElem &val) override
494         int flatIndex = isa->flattenVecElemIndex(reg.index());
496         setVecElemFlat(flatIndex, reg.elemIndex(), val);
497         DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
498                 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
502     setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
504         int flatIndex = isa->flattenVecPredIndex(reg.index());
507         DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
508                 reg.index(), flatIndex, val.print());
517         DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
621     readVecRegFlat(RegIndex reg) const override
623         return vecRegs[reg];
627     getWritableVecRegFlat(RegIndex reg) override
629         return vecRegs[reg];
633     setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
635         vecRegs[reg] = val;
640     readVecLaneFlat(RegIndex reg, int lId) const
642         return vecRegs[reg].laneView<T>(lId);
647     setVecLaneFlat(RegIndex reg, int lId, const LD &val)
649         vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
653     readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
655         return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
659     setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
662         vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
666     readVecPredRegFlat(RegIndex reg) const override
668         return vecPredRegs[reg];
672     getWritableVecPredRegFlat(RegIndex reg) override
674         return vecPredRegs[reg];
678     setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
680         vecPredRegs[reg] = val;